AD9680 datasheet(69/99 Pages) AD

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Data Sheet

AD9680

Rev. C | Page 67 of 97

Table 24. AD9680 Control Characters used in JESD204B

Abbreviation

Control Symbol

8-Bit Value

10-Bit Value,

RD1 = −1

10-Bit Value,

RD1 = +1

Description

/R/

/K28.0/

000 11100

001111 0100

110000 1011

Start of multiframe

/A/

/K28.3/

011 11100

001111 0011

110000 1100

Lane alignment

/Q/

/K28.4/

100 11100

001111 0100

110000 1101

Start of link configuration data

/K/

/K28.5/

101 11100

001111 1010

110000 0101

Group synchronization

/F/

/K28.7/

111 11100

001111 1000

110000 0111

Frame alignment

RD means running disparity.

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9680 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV p-p swing at the receiver

(see Figure 159). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage is DRVDD/2. Otherwise, 0.1 µF ac coupling

capacitors can be used to terminate to any single-ended voltage.

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

OUTPUT SWING = 300mV p-p

0.1µF

100Ω

50Ω

0.1µF

RECEIVER

VCM = VRXCM

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 159. AC-Coupled Digital Output Termination Example

The AD9680 digital outputs can interface with custom ASICs

and FPGA receivers, providing superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible. The

common mode of the digital output automatically biases itself

to half the DRVDD supply of 1.2 V (VCM = 0.6 V). See Figure 160

for dc coupling the outputs to the receiver logic.

SERDOUTx+

DRVDD

SERDOUTx–

OUTPUT SWING = 300mV p-p

100Ω

RECEIVER

VCM = DRVDD/2

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 160. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and at equal lengths.

Figure 161 to Figure 166 show an example of the digital output

data eye, time interval error (TIE) jitter histogram, and bathtub

curve for one AD9680 lane running at 10 Gbps and 6 Gbps,

respectively. The format of the output data is twos complement

by default. To change the output data format, see the Memory Map

section (Register 0x561 in Table 36).

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link can cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it can increase electromagnetic interference (EMI). See

the Memory Map section (Register 0x5C1 to Register 0x5C5 in

Table 36) for more details.

Phase-Locked Loop

The phase-locked loop (PLL) is used to generate the serializer

clock, which operates at the JESD204B lane rate. The status of

the PLL lock can be checked in the PLL locked status bit

(Register 0x56F, Bit 7). This read only bit lets the user know if

the PLL has achieved a lock for the specific setup. The JESD204B

lane rate control, Bit 4 of Register 0x56E, must be set to

correspond with the lane rate.

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