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AD9680 Datasheet(PDF) 73 Page - Analog Devices

Part # AD9680
Description  Dual Analog-to-Digital Converter
PDF  99 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9680 Datasheet(HTML) 73 Page - Analog Devices

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Data Sheet
AD9680
Rev. C | Page 71 of 97
CONFIGURING THE JESD204B LINK
The AD9680 has one JESD204B link. The device offers an easy
way to set up the JESD204B link through the JESD04B quick
configuration register (Register 0x570). The serial outputs
(SERDOUT0± to SERDOUT3±) are considered to be part of
one JESD204B link. The basic parameters that determine the
link setup are
•
Number of lanes per link (L)
•
Number of converters per link (M)
•
Number of octets per frame (F)
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual converter
mapping setup is shown in Figure 168.
The maximum lane rate allowed by the JESD204B specification
is 12.5 Gbps. The lane line rate is related to the JESD204B
parameters using the following equation:
L
f
N
M
Rate
Line
Lane
OUT
×
×
×
=
8
10
'
where
Ratio
Decimation
f
f
CLOCK
ADC
OUT
_
=
The decimation ratio (DCM) is the parameter programmed in
Register 0x201.
The following steps can be used to configure the output:
1. Power down the link.
2. Select quick configuration options.
3. Configure detailed options.
4. Set output lane mapping (optional).
5. Set additional driver configuration options (optional).
6. Power up the link.
If the lane line rate calculated is less than 6.25 Gbps, select
the low line rate option by programming a value of 0x10 to
Register 0x56E.
Table 26 and Table 27 show the JESD204B output configurations
supported for both N΄ = 16 and N΄ = 8 for a given number of
virtual converters. Take care to ensure that the serial line rate
for a given configuration is within the supported range of
3.125 Gbps to 12.5 Gbps.
Table 26. JESD204B Output Configurations for N΄ = 16
Number of Virtual
Converters
Supported
(Same Value as M)
JESD204B Quick
Configuration
(0x570)
JESD204B Serial
Line Rate1
JESD204B Transport Layer Settings2
L
M
F
S
HD
N
N΄
CS
K3
1
0x01
20 × fOUT
1
1
2
1
0
8 to 16
16
0 to 3
Only valid K
values that
are divisible
by 4 are
supported
0x40
10 × fOUT
2
1
1
1
1
8 to 16
16
0 to 3
0x41
10 × fOUT
2
1
2
2
0
8 to 16
16
0 to 3
0x80
5 × fOUT
4
1
1
2
1
8 to 16
16
0 to 3
0x81
5 × fOUT
4
1
2
4
0
8 to 16
16
0 to 3
2
0x0A
40 × fOUT
1
2
4
1
0
8 to 16
16
0 to 3
0x49
20 × fOUT
2
2
2
1
0
8 to 16
16
0 to 3
0x88
10 × fOUT
4
2
1
1
1
8 to 16
16
0 to 3
0x89
10 × fOUT
4
2
2
2
0
8 to 16
16
0 to 3
4
0x13
80 × fOUT
1
4
8
1
0
8 to 16
16
0 to 3
0x52
40 × fOUT
2
4
4
1
0
8 to 16
16
0 to 3
0x91
20 × fOUT
4
4
2
1
0
8 to 16
16
0 to 3
8
0x1C
160 × fOUT
1
8
16
1
0
8 to 16
16
0 to 3
0x5B
80 × fOUT
2
8
8
1
0
8 to 16
16
0 to 3
0x9A
40 × fOUT
4
8
4
1
0
8 to 16
16
0 to 3
1
fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is
≤12.5 Gbps and ≥ 6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the low line
rate mode must be enabled (set Bit 4 to 0x1 in 0x56E).
2
JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3
For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.



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