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AD9680 Datasheet(PDF) 90 Page - Analog Devices |
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AD9680 Datasheet(HTML) 90 Page - Analog Devices |
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90 / 99 page  AD9680 Data Sheet Rev. C | Page 88 of 97 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x276 Signal Monitor Result Register 1 (local) Signal monitor result, Bits[15:8] Read only Updated based on Reg. 0x274[4] 0x277 Signal Monitor Result Register 1 (local) 0 0 0 0 Signal monitor result, Bits[19:16] Read only Updated based on Reg. 0x274[4] 0x278 Signal monitor period counter result (local) Period count result, Bits[7:0] Read only Updated based on Reg. 0x274[4] 0x279 Signal monitor SPORT over JESD204B control (local) 0 0 0 0 0 0 00 = disabled 11 = enable 0x00 0x27A SPORT over JESD204B input selection (local) 0 0 0 0 0 0 Peak detector 0 = disabled 1 = enabled 0 0x00 DDC Function Registers (See the Digital Downconverter (DDC) Section) 0x300 DDC synchro- nization control 0 0 0 DDC NCO soft reset 0 = normal operation 1 = reset 0 0 Synchronization mode (triggered by SYSREF±) 00 = disabled 01 = continuous 11 = one shot 0x310 DDC 0 control Mixer select 0 = real mixer 1 = complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fs/4 downmixing mode) 11 = test mode (mixer inputs forced to +fS, NCO enabled) Complex to real enable 0 = disabled 1 = enabled 0 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 0x311 DDC 0 input selection 0 0 0 0 0 Q input select 0 = Ch A 1 = Ch B 0 I input select 0 = Ch A 1 = Ch B 0x00 Refer to the DDC section 0x314 DDC 0 frequency LSB DDC 0 NCO frequency value, Bits[7:0] twos complement 0x00 0x315 DDC 0 frequency MSB X X X X DDC 0 NCO frequency value, Bits[11:8] twos complement 0x00 0x320 DDC 0 phase LSB DDC 0 NCO phase value, Bits[7:0] twos complement 0x00 0x321 DDC 0 phase MSB X X X X DDC 0 NCO phase value, Bits[11:8] twos complement 0x00 |
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