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AD9680 Datasheet(PDF) 95 Page - Analog Devices |
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AD9680 Datasheet(HTML) 95 Page - Analog Devices |
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95 / 99 page  Data Sheet AD9680 Rev. C | Page 93 of 97 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x574 JESD204B Link Mode Control 4 ILAS delay 0000 = transmit ILAS on first LMFC after SYNCINB± deasserted 0001 = transmit ILAS on second LMFC after SYNCINB± deasserted … 1111 = transmit ILAS on 16th LMFC after SYNCINB± deasserted 0 Link layer test mode 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /D21.5/ characters 100 = modified RPAT test sequence 101 = JSPAT test sequence 110 = JTSPAT test sequence 0x00 0x578 JESD204B LMFC offset 0 0 0 LMFC phase offset value[4:0] 0x00 0x580 JESD204B DID config JESD204B Tx DID value[7:0] 0x00 0x581 JESD204B BID config 0 0 0 0 JESD204B Tx BID value, Bits[3:0] 0x00 0x583 JESD204B LID Config 1 0 0 0 Lane 0 LID value, Bits[4:0] 0x00 0x584 JESD204B LID Config 2 0 0 0 Lane 1 LID value, Bits[4:0] 0x01 0x585 JESD204B LID Config 3 0 0 0 Lane 2 LID value, Bits[4:0] 0x01 0x586 JESD204B LID Config 4 0 0 0 Lane 3 LID value, Bits[4:0] 0x03 0x58B JESD204B parameters SCR/L JESD204B scrambling (SCR) 0 = disabled 1 = enabled 0 0 0 0 0 JESD204B lanes (L) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes Read only, see Register 0x570 0x8X 0x58C JESD204B F config Number of octets per frame, F = Register 0x58C[7:0] + 1 0x88 Read only, see Reg. 0x570 0x58D JESD204B K config 0 0 0 Number of frames per multiframe, K = Register 0x58D[4:0] + 1 Only values where (F × K) mod 4 = 0 are supported 0x1F See Reg. 0x570 0x58E JESD204B M config Number of Converters per Link[7:0] 0x00 = link connected to one virtual converter (M = 1) 0x01 = link connected to two virtual converters (M = 2) 0x03 = link connected to four virtual converters (M = 4) 0x07 = link connected to eight virtual converters (M = 8) Read only 0x58F JESD204B CS/N config Number of control bits (CS) per sample 00 = no control bits (CS = 0) 01 = 1 control bit (CS = 1); Control Bit 2 only 10 = 2 control bits (CS = 2); Control Bit 2 and 1 only 11 = 3 control bits (CS = 3); all control bits (2, 1, 0) 0 ADC converter resolution (N) 0x06 = 7-bit resolution 0x07 = 8-bit resolution 0x08 = 9-bit resolution 0x09 = 10-bit resolution 0x0A = 11-bit resolution 0x0B = 12-bit resolution 0x0C = 13-bit resolution 0x0D = 14-bit resolution 0x0E = 15-bit resolution 0x0F = 16-bit resolution 0x0F 0x590 JESD204B N’ config 0 0 Subclass support (Subclass V) 0 = Subclass 0 (no deter- ministic latency) 1 = Subclass 1 ADC number of bits per sample (N’) 0x7 = 8 bits 0xF = 16 bits 0x2F 0x591 JESD204B S config 0 0 1 Samples per converter frame cycle (S) S value = Register 0x591[4:0] + 1 0x20 Read only |
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