AD9680 datasheet(39/99 Pages) AD

39 / 99 page

Data Sheet

AD9680

Rev. C | Page 37 of 97

and noise performance. These register settings do not impact the

AVDD3 power as much as Register 0x018 does. For frequencies

<500 MHz, it is recommended to use the default settings for

these registers. Table 10 shows the recommended values for the

buffer current control registers for various speed grades.

(>500 MHz for the AD9680-1000). This setting enables the ADC

sampling network to optimize the sampling and settling times

internal to the ADC for high frequency operation. For frequencies

greater than 500 MHz, it is recommended to operate the ADC core

at a 1.46 V full-scale setting irrespective of the speed grade. This

setting offers better SFDR without any significant penalty in SNR.

Figure 118, Figure 119, and Figure 120 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-1250. The recommended settings shown in Table 10

were used to take the data while changing the contents of

INPUT FREQUENCY (MHz)

10.3

147.3

212.3

290.3

355.3

433.3

511.3

589.3

667.3

250MHz

350MHz

450MHz

550MHz

Figure 118. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);

fIN < 500 MHz; Front-End Network Shown in Figure 115

INPUT FREQUENCY (MHz)

602.3

680.3

758.3

836.3

914.3

992.3 1070.3 1148.3 1226.3

350MHz

450MHz

550MHz

650MHz

Figure 119. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);

600 MHz < fIN < 1300 MHz; Front-End Network Shown in Figure 115

INPUT FREQUENCY (MHz)

650MHz

750MHz

850MHz

1304.3

1408.3

1512.3

1616.3

1720.3

1824.3

1928.3

Figure 120. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);

1300 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115

Figure 121, Figure 122, and Figure 123 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-1000. The recommended settings shown in Table 10

were used to take the data while changing the contents of

110

160

210

260

310

360

410

460

ANALOG INPUT FREQUENCY (MHz)

1.5×

3.0×

4.5×

Figure 121. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);

fIN < 500 MHz; Front-End Network Shown in Figure 115

ANALOG INPUT FREQUENCY (MHz)

503.4

677.6

851.9

1026.2

1200.5

1374.8

4.0×

5.0×

6.0×

Figure 122. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);

500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 115

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