AD9680 datasheet(44/99 Pages) AD

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AD9680

Data Sheet

Rev. C | Page 42 of 97

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9680 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

Figure 134 shows a preferred method for clocking the AD9680.

The low jitter clock source is converted from a single-ended

signal to a differential signal using an RF transformer.

ADC

CLK+

CLK–

0.1µF

100Ω

50Ω

CLOCK

INPUT

1:1Z

Figure 134. Transformer-Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 135

and Figure 136.

ADC

CLK+

CLK–

0.1µF

Z0 = 50Ω

33Ω

71Ω

10pF

3.3V

Figure 135. Differential CML Sample Clock

ADC

CLK+

CLK–

0.1µF

50Ω1

100Ω

CLOCK INPUT

LVDS

DRIVER

CLK+

CLK–

50Ω RESISTORS ARE OPTIONAL.

CLOCK INPUT

Figure 136. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. In applications where the clock duty cycle cannot

be guaranteed to be 50%, a higher multiple frequency clock can be

supplied to the device. The AD9680 can be clocked at 2 GHz with

the internal clock divider set to 2. The output of the divider offers

a 50% duty cycle, high slew rate (fast edge) clock signal to the

internal ADC. See the Memory Map section for more details on

using this feature.

Input Clock Divider

The AD9680 contains an input clock divider with the ability to

divide the Nyquist input clock by 1, 2, 4, and 8. The divider

ratios can be selected using Register 0x10B. This is shown in

Figure 137.

The maximum frequency at the CLK± inputs is 4 GHz. This is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, care must be taken to program

the appropriate divider ratio into the clock divider before applying

the clock signal. This ensures that the current transients during

device startup are controlled.

CLK+

CLK–

÷2

÷4

REG 0x10B

÷8

Figure 137. Clock Divider Circuit

The AD9680 clock divider can be synchronized using the

external SYSREF± input. A valid SYSREF± causes the clock

divider to reset to a programmable state. This synchronization

feature allows multiple devices to have their clock dividers

aligned to guarantee simultaneous input sampling. See the

Multichip Synchronization section for more information.

Input Clock Divider ½ Period Delay Adjust

The input clock divider inside the AD9680 provides phase delay

in increments of ½ the input clock cycle. Register 0x10C can be

programmed to enable this delay independently for each channel.

Changing this register does not affect the stability of the

JESD204B link.

Clock Fine Delay Adjust

The AD9680 sampling edge instant can be adjusted by writing to

enables the feature, and Bits[7:0] of Register 0x118 set the value

of the delay. This value can be programmed individually for

each channel. The clock delay can be adjusted from −151.7 ps

to +150 ps in ~1.7 ps increments. The clock delay adjust takes

effect immediately when it is enabled via SPI writes. Enabling

the clock fine delay adjust in Register 0x117 causes a datapath

reset. However, the contents of Register 0x118 can be changed

without affecting the stability of the JESD204B link.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (fA) due only to aperture jitter (tJ) can be calculated by

SNR = 20 × log 10 (2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications.

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