AD9680 datasheet(47/99 Pages) AD

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Data Sheet

AD9680

Rev. C | Page 45 of 97

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

The results of the signal monitor block can be obtained either

by reading back the internal values from the SPI port or by

embedding the signal monitoring information into the

JESD204B interface as special control bits. A global, 24-bit

programmable period controls the duration of the

measurement. Figure 142 shows the simplified block diagram

of the signal monitor block.

FROM

MEMORY

MAP

DOWN

COUNTER

COUNT = 1?

MAGNITUDE

STORAGE

FROM

INPUT

SIGNAL

MONITOR

HOLDING

LOAD

CLEAR

COMPARE

A > B

LOAD

TO SPORT OVER

JESD204B AND

MEMORY MAP

SIGNAL MONITOR

PERIOD REGISTER

(SMPR)

0x271, 0x272, 0x273

Figure 142. Signal Monitor Block

The peak detector captures the largest signal within the

observation period. The detector only observes the magnitude

of the signal. The resolution of the peak detector is a 13-bit

value, and the observation period is 24 bits and represents

converter output samples. The peak magnitude can be derived

by using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)

The magnitude of the input port signal is monitored over a

programmable time period, which is determined by the signal

monitor period register (SMPR). The peak detector function is

enabled by setting Bit 1 of Register 0x270 in the signal monitor

control register. The 24-bit SMPR must be programmed before

activating this mode.

After enabling peak detection mode, the value in the SMPR is

loaded into a monitor period timer, which decrements at the

decimated clock rate. The magnitude of the input signal is

compared with the value in the internal magnitude storage

is updated as the current peak level. The initial value of the

magnitude storage register is set to the current ADC input signal

magnitude. This comparison continues until the monitor period

timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

through the SPORT over the JESD204B interface. The monitor

period timer is reloaded with the value in the SMPR, and the

countdown restarts. In addition, the magnitude of the first

input sample is updated in the magnitude storage register, and

the comparison and update procedure, as explained previously,

continues.

AD9680 Datasheet(PDF) 47 Page - Analog Devices

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