AD9680 datasheet(12/99 Pages) AD

12 / 99 page

AD9680

Data Sheet

Rev. C | Page 10 of 97

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

See Figure 3

tSU_SR

Device clock to SYSREF+ setup time

117

tH_SR

Device clock to SYSREF+ hold time

−96

SPI TIMING REQUIREMENTS

See Figure 4

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and output

data valid for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in Figure 4)

Timing Diagrams

SERDOUT0–

N – 54

N – 53

N – 52

N – 51

N – 1

SAMPLE N

N + 1

APERTURE

DELAY

N – 55

CLK+

CLK–

CLK+

CLK–

SERDOUT0+

SERDOUT1–

SERDOUT1+

SERDOUT2–

SERDOUT2+

SERDOUT3–

SERDOUT3+

CONVERTER0 MSB

CONVERTER0 LSB

CONVERTER1 MSB

CONVERTER1 LSB

ANALOG

INPUT

SIGNAL

SAMPLE N – 55

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

SAMPLE N – 54

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

SAMPLE N – 53

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)

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