AD9680 datasheet(48/99 Pages) AD

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AD9680

Data Sheet

Rev. C | Page 46 of 97

SPORT OVER JESD204B

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

The signal control monitor function is enabled by setting Bits[1:0]

of Register 0x279 and Bit 1 of Register 0x27A. Figure 143 shows

two different example configurations for the signal monitor

control bit locations inside the JESD204B samples. A maximum

of three control bits can be inserted into the JESD204B samples;

however, only one control bit is required for the signal monitor.

Control bits are inserted from MSB to LSB. If only one control bit

is to be inserted (CS = 1), only the most significant control bit is

used (see Example Configuration 1 and Example Configuration 2

in Figure 143). To select the SPORT over JESD204B option,

program Register 0x559, Register 0x55A, and Register 0x58F.

See Table 36 for more information on setting these bits.

Figure 144 shows the 25-bit frame data that encapsulates the

peak detector value. The frame data is transmitted MSB first

with five 5-bit subframes. Each subframe contains a start bit

that can be used by a receiver to validate the deserialized data.

Figure 145 shows the SPORT over JESD204B signal monitor

data with a monitor period timer set to 80 samples.

14-BIT CONVERTER RESOLUTION (N = 14)

TAIL

CONTROL

BIT

(CS = 1)

1-BIT

CONTROL

BIT

(CS = 1)

1 TAIL

BIT

SERIALIZED SIGNAL MONITOR

FRAME DATA

EXAMPLE

CONFIGURATION 1

(N' = 16, N = 15, CS = 1)

EXAMPLE

CONFIGURATION 2

(N' = 16, N = 14, CS = 1)

SERIALIZED SIGNAL MONITOR

FRAME DATA

16-BIT JESD204B SAMPLE SIZE (N' = 16)

S[13]

S[12]

S[11]

S[10]

S[9]

S[8]

S[7]

S[6]

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

CTRL

[BIT 2]

CTRL

[BIT 2]

S[14]

S[13]

S[12]

S[11]

S[10]

S[9]

S[8]

S[7]

S[6]

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

15-BIT CONVERTER RESOLUTION (N = 15)

16-BIT JESD204B SAMPLE SIZE (N' = 16)

Figure 143. Signal Monitor Control Bit Locations

25-BIT

FRAME

5-BIT IDLE

SUB-FRAME

(OPTIONAL)

5-BIT IDENTIFIER

SUB-FRAME

5-BIT DATA

MSB

SUB-FRAME

5-BIT DATA

SUB-FRAME

5-BIT DATA

SUB-FRAME

5-BIT DATA

LSB

SUB-FRAME

5-BIT SUB-FRAMES

P[] = PEAK MAGNITUDE VALUE

IDLE

START

P[0]

START

P[4]

P[3]

P[2]

P1]

START

P[8]

P[7]

P[6]

P5]

START

P[12]

P[11]

P[10]

P[9]

START

ID[3]

ID[2]

ID[1]

ID[0]

Figure 144. SPORT over JESD204B Signal Monitor Frame Data

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