ST2202 datasheet(21/65 Pages) ETC

21 / 65 page

Sitronix

ST2202

Ver 2.0a

21/65

2003-May-05

OSCK

SYSCK

OSC

OSTP(SYS[6])

OUT

OSCX

XSTP(SYS[5])

OUT

SEL

WSKP(SYS[3])

CLK32

MUX2

IN0

IN1

XBAK(SYS[4])

Heavy

XSEL(SYS[7])

Warm-up control

256 cycles

16 cycles

Normal

•

LCDCK

Divider

LCKR[4:0]

OUT

OSCK,OSCK/2/4…/30

OSCK, CLK32

XSEL(SYS[7])

INA

OUT

INB

PSGCK

Divider

PSGC[6:4]

•

PSGCK

•

OSCKx2,OSCK/2/4/8/16

CLK32

BGR

Integer

Divider

BGRCK

REF

Target

BDIV[7:0]

BSR[7:0] / BCTR[2:0]

OUT

CLK32xK

•

SPICK

Divider

SCKR[6:4]

OUT

OSCK/2/4/8…/256

FIGURE 11-1 Clock Generator Diagram

TABLE 11-2 System Control Register (SYS)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

XSEL

OSTP

XSTP

XBAK

WSKP

WAIT

IRREN

HIGH

0000 0001

$030

SYS

XSEL

OSTP

XSTP

XBAK

WSKP

WAIT

IRREN

LVDEN

0000 0000

Bit 7: XSEL : Write: Select source of system clock (SYSCK) / Read: report of clock source being used

0 = OSC

1 = OSCX

Bit 6: OSTP : OSC stop control bit

0 = Enable OSC

1 = Disable OSC

Bit 5: XSTP : OSCX stop control bit

0 = Enable OSCX

1 = Disable OSCX

Bit 4: XBAK : OSCX driver heavy load bit

0 = OSCX heavy load

1 = OSCX normal load

Bit 3: WSKP : System warm-up cycles selection bit

0 = 256 warm-up cycles

1 = 16 warm-up cycles

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