ST2202 datasheet(14/65 Pages) ETC

14 / 65 page

Sitronix

ST2202

Ver 2.0a

14/65

2003-May-05

9.. G

PIIO

The ST2202 consists of 48 general-purpose I/O (GPIO) which

are divided into six I/O ports: Port-A/B/C/D/E and Port-L.

Control registers of GPIO are shown as following and in TABLE

9-1.

Port data registers: PA~PE, PL

Port direction control registers: PCA~PCE, PCL

Port type select registers: PSC

Port function select registers: PFC and PFD

Port miscellaneous control register: PMCR

TABLE 9-1 Summary Of Control Registers Of GPIO

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$000

R/W

PA[7]

PA[6]

PA[5]

PA[4]

PA[3]

PA[2]

PA[1]

PA[0]

1111 1111

$001

R/W

PB[7]

PB[6]

PB[5]

PB[4]

PB[3]

PB[2]

PB[1]

PB[0]

1111 1111

$002

R/W

PC[7]

PC[6]

PC[5]

PC[4]

PC[3]

PC[2]

PC[1]

PC[0]

1111 1111

$003

R/W

PD[7]

PD[6]

PD[5]

PD[4]

PD[3]

PD[2]

PD[1]

PD[0]

1111 1111

$004

R/W

PE[7]

PE[6]

PE[5]

PE[4]

PE[3]

PE[2]

PE[1]

PE[0]

1111 1111

$04C

R/W

PL[7]

PL[6]

PL[5]

PL[4]

PL[3]

PL[2]

PL[1]

PL[0]

1111 1111

$005

PSC

R/W

PSC[7]

PSC[6]

PSC[5]

PSC[4]

PSC[3]

PSC[2]

PSC[1]

PSC[0]

1111 1111

$008

PCA

R/W

PCA[7]

PCA[6]

PCA[5]

PCA[4]

PCA[3]

PCA[2]

PCA[1]

PCA[0]

0000 0000

$009

PCB

R/W

PCB[7]

PCB[6]

PCB[5]

PCB[4]

PCB[3]

PCB[2]

PCB[1]

PCB[0]

0000 0000

$00A

PCC

R/W

PCC[7]

PCC[6]

PCC[5]

PCC[4]

PCC[3]

PCC[2]

PCC[1]

PCC[0]

0000 0000

$00B

PCD

R/W

PCD[7]

PCD[6]

PCD[5]

PCD[4]

PCD[3]

PCD[2]

PCD[1]

PCD[0]

0000 0000

$00C

PCE

R/W

PCE[7]

PCE[6]

PCE[5]

PCE[4]

PCE[3]

PCE[2]

PCE[1]

PCE[0]

0000 0000

$04E

PCL

PCL[7]

PCL[6]

PCL[5]

PCL[4]

PCL[3]

PCL[2]

PCL[1]

PCL[0]

0000 0000

$00D

PFC

R/W

RXD0

TXD0

SRDY

MOSI

MISO

SCK

INTX

0000 0000

$00E

PFD

R/W

RXD1

TXD1

CS6

CS5

CS4

CS3

CS2

CS1

0000 0000

$00F

PMCR

R/W

PULL

PDBN

INTEG

CSM1

CSM0

BCO

TCO1

TCO0

1000 0000

Each single pin can be programmed to be input or output. This

is controlled by port direction control registers PCx. Setting bit

of PCx makes respective pin to output, and clearing this bit for

input. There are two options: pull-up/down for inputs of Port-C

but only pull-up for inputs of the other ports. In case of output,

there are open-drain/CMOS options for outputs of PortC but

only CMOS for the other ports. Refer to TABLE 9-2.

TABLE 9-2 I/O Types Of GPIO Ports

I/O Types

I/O Mode

Port-A/B/D/E/L

Port-C

Input

Pull-up/Pure

Pull-up/Pull-down/Pure

Output

CMOS

Open-drain/CMOS

Input Mode

In case of input function, port data registers Px reflect the

values on associated pins. Besides read instruction for data of

signals input, writing to register Px selects I/O types of pins,

pull-up or pull-down. Setting bits of all port data register Px to

select pull-up type. Clearing bits of only PC to select pull-down

type for pins of Port-C. There are no pull-down resistors for

Port-A/B/D/E and Port-L, thereby no pull-down resistors will be

enabled if clearing bits of PA, PB, PD, PE and PL. Pull-up

resistors of Port-A/B/D/E/L are also controlled by PULL bit (bit7

of port miscellaneous register PMCR), “0” is to disable, while

“1” is to enable them. The pull-up/pull-down resistors of Port-C

are further controlled by bits of port type select registers PSC.

They work in the same way with PULL bit of PMCR but only on

single pin, “0” is to disable, while “1” is to enable. Refer to

FIGURE 9-1.

VCC

PORT

DATA

( PDR )

PULL-UP

PMOS

PULL-UP

RD_INPUT

DATA INPUT

PORT

CONTROL

( PCR )

FIGURE 9-1 Configuration Of Inputs

Output Mode

In case of output function, Write to port data registers Px

makes pins to output desired value. This value can also be

read back by read instruction. Besides Port-C, the output pins

are CMOS type. Port-C have two options of output types:

open-drain and CMOS, and is controlled by port type select

registers PSC. Clearing bits of registers PSC is for that disable

PMOS of output stage and left only NMOS, while setting bits is

for CMOS. Refer to FIGURE 9-2.

FIGURE 9-2 Configuration Of Outputs

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