ST2202 datasheet(12/65 Pages) ETC

12 / 65 page

Sitronix

ST2202

Ver 2.0a

12/65

2003-May-05

8.. IIN

T C

The ST2202 supports 11 hardware internal/external interrupts

as well as one software interrupt Brk. There are 12 exception

vectors for these interrupts and another one for reset. All

interrupts are controlled by interrupt disable flag “I” (bit2 of

status register P), and initiate if “I” equals “0”. Hardware

interrupts are further controlled by interrupt enable register

IENA. Setting bits of IENA enables respective interrupts.

The interrupt controller owns one priority arbitrator. When more

than one interrupts happen at the same time, the one with

lower priority number will be executed first. Refer to TABLE 8-1

for priorities of interrupts.

Once an interrupt event was enabled and then happens, the

CPU wakes up (if in either wait mode), and associated bit of

interrupt request register (IREQ) will be set. If “I” flag is cleared,

the related vector will be fetched and then the interrupt service

routine (ISR) will be executed. Interrupt request flag can be

cleared by two methods. One is to write “0” to IREQ, the other

is to initiate related interrupt service routine. Hardware will

automatically clear the Interrupt request flag. All interrupt

vectors are listed in TABLE 8-1.

TABLE 8-1 Interrupt Vectors

Name

Signal Source

Vector Address

Priority

Description

BRK

Internal

$7FFF,$7FFE

Software BRK operation vector

RESET

External

$7FFD,$7FFC

Reset vector

$7FFB,$7FFA

Reserved

INTX

External

$7FF9,$7FF8

PC0 edge interrupt

DAC

Internal

$7FF7,$7FF6

Reload DAC data interrupt

Internal/External

$7FF5,$7FF4

Timer0 interrupt

Internal/External

$7FF3,$7FF2

Timer1 interrupt

External

$7FF1,$7FF0

Port-A transition interrupt

Internal

$7FEF,$7FEE

Base Timer interrupt

LCD

Internal

$7FED,$7FEC

LCD Frame interrupt

$7FEB,$7FEA

Reserved

STX

External

$7FE9,$7FE8

SPI transmit buffer empty interrupt

SRX

External

$7FE7,$7FE6

SPI receive buffer ready interrupt

UTX

External

$7FE5,$7FE4

UART receiver interrupt

URX

External

$7FE3,$7FE2

UART transmitter interrupt

TABLE 8-2 Interrupt Request Register (IREQ)

Address Name

R/W

Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10

Bit 1/9

Bit 0/8

Default

$03C

IREQL

R/W

IRLCD

IRBT

IRPT

IRT1

IRT0

IRDAC

IRX

-000 0000

$03D

IREQH

R/W

IRURX

IRUTX

IRSRX

IRSTX

- - - - 0000

Bit 0: IRX: INTX interrupt request bit

1 = INTX edge interrupt occurs

0 = INTX edge interrupt doesn’t occur

Bit 1: IRDAC: DAC reload interrupt request bit

1 = DAC time out interrupt occurs

0 = DAC time out interrupt doesn’t occur

Bit 2: IRT0: Timer0 interrupt request bit

1 = Timer0 overflow interrupt occurs

0 = Timer0 overflow interrupt doesn’t occur

Bit 3: IRT1: Timer1 interrupt request bit

1 = Timer1 overflow interrupt occurs

0 = Timer1 overflow interrupt doesn’t occur

Bit 4: IRPT: Port-A interrupt request bit

1 = Port-A transition interrupt occurs

0 = Port-A transition interrupt doesn’t occur

Bit 5: IRBT: Base Timer interrupt request bit

1 = Time base interrupt occurs

0 = Time base interrupt doesn’t occur

Bit 6: IRLCD: LCD frame Interrupt request bit

1 = LCD Frame interrupt occurs

0 = LCD Frame interrupt doesn’t occur

Bit 8: IRSTX: SPI transmitter interrupt request bit

1 = SPI transmit buffer is empty

0 = SPI transmit buffer is occupied

Bit 9: IRSRX: SPI receiver interrupt request bit

1 = SPI receive buffer is ready

0 = SPI receive buffer is not ready

Bit 10: IRUTX: UART transmitter interrupt request bit

1 = UART data transmission completes

0 = UART data transmission not completes

Bit 11: IRURX: UART receiver interrupt request bit

1 = UART data receiving completes

0 = UART data receiving not completes

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