ST2202 datasheet(59/65 Pages) ETC

59 / 65 page

Sitronix

ST2202

Ver 2.0a

59/65

2003-May-05

1.. W

G T

TIIM

The watchdog timer (WDT) is an added check that a

program is running and sequencing properly. When the

application software is running, it is responsible for keeping

the 2- or 8-second watchdog timer from timing out. If the

watchdog timer times out, it is an indication that the

software is no longer being executed in the intended

sequence. At this time the watchdog timer generates a

reset signal to the system.

21.1 WDT Operations

The WDT is enabled by setting the WDT enable flag

WDTEN (MISC[3]). Two time settings, 2 and 8 seconds,

are selectable with selection bit WDTPS (MISC[2]).WDT is

clocked by the 2Hz clock from the base timer and therefore

has 0.5-second resolution. It is recommended that the

watchdog timer be periodically cleared by software once it

is enabled. Otherwise, software reset will be generated

when the timer reached a binary value of 4 or 16.

Note:The WDT can be reset by writing any value

to MISC register.

After a system reset, WDTEN is cleared. Then the

WDT returns to be idle.

TABLE 21-1 System Miscellaneous Register (MISC)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

WDTEN WDTPS

TEST

- - - - 0000

$038

MISC

Reset WDT

Bit 2: WDTPS : WDT time-out time selection bit

0 = 8 seconds

1 = 2 seconds

Bit 3: WDTEN : WDT control bit

0 = Disable WDT

1 = Enable WDT

Bit 1~0: TEST : These two bits should be both zero in normal operation

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