ST2202 datasheet(47/65 Pages) ETC

47 / 65 page

Sitronix

ST2202

Ver 2.0a

47/65

2003-May-05

will be shifted in as well. After the exchanged bits reach bit

count setting, current data is complete and then moves to

receive buffer.

The exchange continues with auto reload function of shift

be sent out and be received in right after the LSB of the

previous one with no pause.

After the exchange was triggered, the slave-select signal

SS (PC4) outputs low level to enable the external slave

device. It keeps at low level during exchanges of data and

data, and returns to high when exchanges cease.

Slave Mode

In slave mode, SS (PC5) and SCK (PC1) become input,

while DATA_READY (PC5) is not functional. The exchange

takes place only when SS inputs low level and ends when

it returns to high. On the falling edge of SS , the shift

the exchange initiates. During exchanging, data is clocked

by external clock from SCK and is shifted in and out the

shift register. Exchanged data will be ready when the

exchanged bit number matches bit count setting. After data

is ready, data transfer between shift register and two buffers

will function automatically as it does in master mode. So

that the shift register can be ready for the succeeding clock

edge. If SS rises before enough data bits, current

exchange is over anyway, but the bit count violation flag

BERR (SSR[0]) will be set.

17.1.4 SPI Interrupts

Four interrupts are supported by SPI with two interrupt

vectors.

Transmit buffer empty interrupt happens when a data

exchange starts and the transmit buffer is empty. This

status can be read from status bit TXEMP (SSR[5]).

Receive buffer ready interrupt happens when a data

exchange completes and the receive buffer is filled with one

new data. This interrupt is enabled by setting control bit

RXIEN (SCTR[6]). The status is reported at status bit

RXRDY (SSR[6]).

The other two interrupts are error interrupts and are both

enabled by control bit ERIEN (SCTR[5]). Receive buffer

overrun interrupt and bit count violation interrupt share the

interrupt vector with receive buffer ready interrupt. These

three interrupts are “OR” together to generate an individual

vector. In master mode, receive buffer overrun interrupt

happens when moving new data from shift register to

receive buffer with RXRDY equals “1”. The overrun interrupt

is issued and the status bit OERR (SSR[1]) will be set. In

slave mode, old data in receive buffer will not be flushed

while other operations are the same with those in master

mode.

Bit count violation interrupt only happens in slave mode. If

SS input rises before enough data bits are reached,

current exchange is over anyway, but the bit count violation

flag BERR (SSR[0]) will be set and the interrupt is issued.

17.2 Interface Signals

Five multiplexed signals are used to interface with other SPI

devices. With setting related bits of port function select

function select bits should be ascertained before they are

used. Refer to section 9 for these settings.

SCK (PC1)

This is a bidirectional SPI synchronous clock I/O, which is

multiplexed with PC1. SCK is output in master mode and

input in slave mode.

MISO (PC2)

Master In/Slave Out bidirectional signal, which is

multiplexed with PC2. External data is inputted to this pin to

the shift register in master mode. In slave mode, it is an

output of shift register.

MOSI (PC3)

Master Out/Slave In bidirectional signal, which is

multiplexed with PC3. Data in shift register is outputted from

this pin in master mode. In slave mode, it is an input of

external data to the shift register.

SS (PC4)

SS is a bidirectional slave-select signal, which is

multiplexed with PC4. In master mode, SS is output to

enable a slave device. In slave mode, SS is inputted a low

level to trigger the exchange.

DATA_READY (PC5)

DATA_READY is an input signal, which is multiplexed with

PC5. It is used only in master mode and can be a GPIO in

slave mode. The operation of DATA_READY can be

enabled by setting PFC[5]. The default active level is high,

and can be inverted by setting DRINV (SCTR[3]). Active

level is inputted to indicate that the communicating slave is

ready for data exchange.

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