ST2202 datasheet(25/65 Pages) ETC

25 / 65 page

Sitronix

ST2202

Ver 2.0a

25/65

2003-May-05

12.1.2 PRES

The prescaler PRES is an 8-bits counter as shown in FIGURE

12-1. Which provides four clock sources for base timer and

timer1, and it is controlled by register PRS. The instruction read

toward PRS will bring out the content of PRES and the

Instruction write toward PRS will reset, enable or select clock

sources for PRES.

When user set external interrupt as the input of PRES for event

counter, combining PRES and Timer1 will get a 16bit-event

counter.

TABLE 12-2 Prescaler Control Register (PRS)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

PRS[7]

PRS[6]

PRS[5]

PRS[4]

PRS[3]

PRS[2]

PRS[1]

PRS[0]

0000 0000

$023

PRS

SRES

SENA

SENT

000 - - - - -

READ

Bit 7~0: PRS[7~0] : Value of PRES counter

WRITE

Bit 7:

SRES : Prescaler Reset bit

Write “1” to reset the prescaler (PRS[7~0])

Bit 6:

SENA : Prescaler enable bit

0 = Disable prescaler counting

1 = Enable prescaler counting

Bit 5:

SENT : Clock source(TCLK) selection for prescaller PRES

0 = Clock source from system clock “SYSCK”

1 = Clock source from external events “INTX”

12.1.3 PREW

The prescaler PREW is an 8-bits counter as shown in Figure

11-6. PREW provides four clocks source for base timer and

timer1. It stops counting only if OSCX stops or hardware reset

occurs.

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