ST2202 datasheet(55/65 Pages) ETC

55 / 65 page

Sitronix

ST2202

Ver 2.0a

55/65

2003-May-05

9.. D

DIIR

T M

Y A

S ((D

A))

To speed up the memory access of this system, a

sequential direct memory access (DMA) controller is

designed-in. DMA can perform memory transfer function

more efficient than CPU does. While DMA working, data

ROM register (DRR) will disable and DMA use DMA

memory bank register (DMR) to access ROM. After DMA

complete, ROM bank control still return to DRR.

With the help of DMR can make DMS across bank

boundary smoothly, but DMR is only valid for DMS. The

DMR can automatic increases when DMS across bank

boundary.

Note: Location of source data can not fall in the range

of internal SRAM( that is the range of

0100H~FFFH).

LCD

DMA

CPU

SRAM

ROM

LCD_CTL

FIGURE 19-1 System Block Diagram

19.1 DMA Control Register

The control register is shown as following:

TABLE 19-2 DMA Control Register (LCTL)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$028

DMSL

DMS[7]

DMS[6]

DMS[5]

DMS[4]

DMS[3]

DMS[2]

DMS[1]

DMS[0] ???? ????

$029

DMSH

DMS[15] DMS[14] DMS[13] DMS[12] DMS[11]

DMS[10]

DMS[9]

DMS[8] ???? ????

$02A

DMDL

DMD[7]

DMD[6]

DMD[5]

DMD[4]

DMD[3]

DMD[2]

DMD[1] DMD[0] ???? ????

$02B

DMDH

DMD[15] DMD[14] DMD[13] DMD[12] DMD[11] DMD[10] DMD[9] DMD[8] ???? ????

$02C

DCNTL

DCNT[7] DCNT[6] DCNT[5] DCNT[4] DCNT[3] DCNT[2] DCNT[1] DCNT[0] ???? ????

$02D

DCNTH

DMAM DCNT[11] DCNT[10] DCNT[9] DCNT[8] - - -? ????

$036

DMRL

R/W

DMR[7]

DMR[6]

DMR[5]

DMR[4]

DMR[3]

DMR[2]

DMR[1] DMR[0] 0000 0000

$037

DMRH

R/W

DMR[10] DMR[9] DMR[8]

- - - - -000

DMS[15:0] : DMA source data starting address register

DMD[15:0]:

DMA destination data starting address register

DCNT[11:0]: DMA moving data byte counter register

DMR[10:0]:

DMA source data bank register (DMR works only when DMS is in the range from 8000h to FFFFh).

DMAM (DCNTH[4]): DMA destination address increasing mode selection bit

0 = Destination address increases automatically.

1 = Destination address is fixed.

The DMA always move (DCNT+1) bytes of data. DMA will

start right after CPU write data into register DCNTL. During

the DMA operation, the CPU hold, until the DMA transfer

completed. The DMR register reset to “$00” on real chip,

but Emulation Board is “unknown”, so recommend initial

DMR register before use. Before Read/Write you have to

initial the PRR, DRR, DMR register when system reset.

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