ST2202 datasheet(51/65 Pages) ETC

51 / 65 page

Sitronix

ST2202

Ver 2.0a

51/65

2003-May-05

FIGURE 18-2 NRZ ASCII “S” with Odd Parity

FIGURE 18-3 IrDA ASCII “S” with Odd Parity

Two kinds of character, 7-bit and 8-bit, are supported by

ST2202. This is controlled by mode selection bit UMOD

(UCTR[1]). Parity options are controlled by parity enable bit

PEN (UCTR[3]) and parity mode selection bit PMOD

(UCTR[2]). Other operations for transmitter and receiver

are described below.

18.2.3 Transmitter Operation

Transmitter operation is controlled by control bit TXEN

(USTR[0]). The transmitter accepts a character from the

CPU bus, and then transmits it immediately after triggered

by writing “1” to control bit TXTRG (USTR[1]). When a

character is available for transmission, the start, stop, and

parity (if enabled) bits are added into the character, and

then it is serially shifted (LSB first) at the selected bit rate.

While transmitter is busy, the busy status is reported at

TXBZ (USTR[1]) with logic value “1”. After all data bits are

finished, IRUTX (IREQ[10]) will be set to issue the interrupt

request. Next data transmission may continue with setting

trigger bit TXTRG again.

If the transmit buffer is empty, the transmitter outputs a

continuous idle (which is “1” for normal polarity). Moreover

a continuous “0” can also be outputted as a break character

by setting BRK bit (UCTR[0]) and then set the trigger bit.

18.2.4 Receiver Operation

Receiver operation is controlled by control bit RXEN

(USTR[2]). Once the receiver is enabled, it searches for a

start bit, qualifies it, and then samples the succeeding data

bits at the perceived bit center. Jitter tolerance and noise

immunity are provided by sampling 16 times per bit and

using a voting circuit to enhance sampling. While receiving,

the busy status of receiver can be read from RXBZ

(USTR[3]) with logic level “1”.

Receiving activity will be complete after the stop bit is

detected. Then IRURX (IREQ[11]) will be set to issue the

interrupt request. The received data can be obtained by

reading data register UDATA. Then the receive trigger bit

RXTRG (USTR[3]) should be set to indicate that the data

Three kinds of errors may arise from illegal received data,

which are reported at 3 bits of status register USTR[6:4]

and are discussed below.

1. Buffer Overrun Error

This error indicates that the receive trigger bit was not set

and the receiver overwrote data in receive buffer, i.e., the

previous character was lost. This also means the software

is not keeping up with the incoming data rate. Error is

updated and reported by reading OER (USTR[4]) for

current received character.

2. Parity Error

If parity is enabled, the parity bit of current received

character is checked and the status is updated in register

bit PER (USTR[5]).

3. Framing Error

This error indicates that a framing error is detected and

there may be corrupted data with missing stop bit. Error is

updated and reported by reading FER (USTR[6]) for current

received character.

18.3 Interface Signals

Two sets of data lines can be enabled simultaneously for

communication, TXD0(PC6), RXD0(PC7) and the auxiliary

pins TXD1(PD6), RXD1(PD7). Data can inputs and outputs

from and to these pins. With setting related bits of port

function select registers (PFC and PFD), signals of the

external devices can be connected. Data in and from these

communication I/Os can be inverted by setting polarity

control bit RXINV and TXINV (IRCTR[7:6]). Direction

settings and function select bits should be ascertained

before using signals. Refer to section 9 for these settings.

TXD0 (PC6)/TXD1 (PD6)

The UART transmit data signal is output to one or both of

these two pins, which are multiplexed with PC6 and PD6.

These pins connect to standard RS-232 or infrared

transceiver modules.

RXD0 (PC7)/RXD1 (PD7)

The UART receive data signal is input from one or both of

these two pins, which are multiplexed with PC7 and PD7. If

RXD0 and RXD1 are enabled at a time, both signals will be

gated with AND logic to produce one single signal. These

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