ST2202 datasheet(13/65 Pages) ETC

13 / 65 page

Sitronix

ST2202

Ver 2.0a

13/65

2003-May-05

TABLE 8-3 Interrupt Enable Register (IENA)

Address Name

R/W

Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10

Bit 1/9

Bit 0/8

Default

$03E

IENAL

R/W

IELCD

IEBT

IEPT

IET1

IET0

IEDAC

IEX

- 000 0000

$03F

IENAH

R/W

IEURX

IEUTX

IESRX

IESTX

- - - - 0000

Bitx: 1 = Enable respective interrupt

0 = Disable respective interrupt

8.1 Interrupt Description

Brk

Instruction ‘BRK’ will cause software interrupt when interrupt

disable flag (I) is cleared. Hardware will push ‘PC’, ‘P ’

registers to stack and then sets interrupt disable flag (I).

Program counter will be loaded with the BRK vector from

locations $7FFE and $7FFF.

Reset

A positive transition of RESET pin will make an initialization

sequence to begin. After the system has been operating, one

low level signal on this line of at least two clock cycles will

cease ST2202 activity. When a positive edge is detected, there

is an initialization sequence lasting six clock cycles. Then the

interrupt disable flag is set, the decimal mode is cleared and

the program counter will be loaded with the reset vector from

locations $7FFC (low byte) and $7FFD (high byte). This is the

start location for program flow. This input should be high in

normal operation.

INTX Interrupt

The IRX (INTX interrupt request) flag will be set while INTX

edge signal occurs. The INTX interrupt will be active when IEX

(INTX interrupt enable) is set, and interrupt disable flag is

cleared. Hardware will push ‘PC’, ‘P ’ registers to stack and

sets interrupt disable flag (I). Program counter will be loaded

with the INTX vector from locations $7FF8 and $7FF9.

DAC Interrupt

The IRDAC (DAC interrupt request) flag will be set while reload

signal of DAC occurs. Then the DAC interrupt will be executed

if IEDAC (DAC interrupt enable) is set, and interrupt disable

flag is cleared. Hardware will push ‘PC’, ‘P ’ Register to stack

and set interrupt mask flag (I). Program counter will be loaded

with the DAC vector from locations $7FF6 and $7FF7.

T0 Interrupt

The IRT0 (TIMER0 interrupt request) flag will be set while

Timer0 overflows. With IET0 (TIMER0 interrupt enable) being

set, the T0 interrupt will execute, and interrupt mask flag will be

cleared. Hardware will push ‘PC’, ‘P ’ Register to stack and

set interrupt mask flag (I). Program counter will be loaded with

the T0 vector from locations $7FF4 and $7FF5.

T1 Interrupt

The IRT1 (TIMER1 interrupt request) flag will be set while T1

overflows. With IET1 (TIMER1 interrupt enable) being set, the

T1 interrupt will execute, and interrupt mask flag will be cleared.

Hardware will push ‘PC’, ‘P ’ Register to stack and set

interrupt mask flag (I). Program counter will be loaded with the

T1 vector from locations $7FF2 and $7FF3.

PT Interrupt

The IRPT (Port-A interrupt request) flag will be set while Port-A

transition signal occurs. With IEPT (PT interrupt enable) being

set, the PT interrupt will be execute, and interrupt mask flag will

be cleared. Hardware will push ‘PC’, ‘P ’ Register to stack and

set interrupt mask flag (I). Program counter will be loaded with

the PT vector from locations $7FF0 and $7FF1.

BT Interrupt

The IRBT (Base timer interrupt request) flag will be set when

Base Timer overflows. The BT interrupt will be executed once

the IEBT (BT interrupt enable) is set and the interrupt mask flag

is cleared. Hardware will push ‘PC’, ‘P ’ Register to stack and

set interrupt mask flag (I). Program counter will be loaded with

the BT vector from locations $7FEE and $7FEF.

LCD Frame Interrupt

The IRLCD (LCD frame interrupt request) flag will be set when

one new display frame cycle starts. This interrupt is very useful

for software grayscale design. The LCD frame interrupt will be

executed once the IELCD (LCD frame interrupt enable) is set

and the interrupt mask flag is cleared. Hardware will push PC

and P registers to stack and set interrupt disable flag “I”.

Program counter PC will be loaded with the LCD vector from

locations $7FEC and $7FED.

SPI Interrupt

There are two interrupts for SPI transmitter and receiver

respectively. IRSTX (SPI transmitter interrupt request) flag will

be set when SPI transmit buffer is empty. IRSRX (SPI receiver

interrupt request) flag will be set when SPI completes one

receiving data and the receive buffer is ready. The SPI

interrupts will be executed once the related enable flag IESRX,

IESTX are set and the interrupt disable flag “I” is cleared.

Hardware will push ‘PC’, ‘P ’ registers to stack and set “I” flag.

Program counter will be loaded with the SPI vector from

locations $7FE7, $7FE6, and $7FE9, $7FE8.

UART Interrupts

There are 2 interrupts for UART: receiver interrupt (URX), and

transmitter interrupt (UTX). URX happens when receive-data is

ready and the receiver needs to be serviced. UTX happens

when current transmission is completed. Errors are indicated by

bits of UART status register (USTR). Other sequences of UART

interrupts are the same with those descriptions above.

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