ST2202 datasheet(8/65 Pages) ETC

8 / 65 page

Sitronix

ST2202

Ver 2.0a

8/65

2003-May-05

7.. M

Y C

FIIG

TIIO

7.1 Memory map

The logical memory space of ST2202 is divided into 3 parts:

$0000~$0FFF (4K), $4000~$7FFF (16K), and $8000~FFFF

(32K). First is for control registers, stack and system memory.

Second and third are banked areas. Logical address in these

two areas combines two bank registers, PRR and DRR

respectively, and then be mapped to a physical address. PRR

is the Program ROM Bank Register and is 12-bit long, while

DRR is the Data ROM Bank Register of the length of 11 bits.

Both can refer to a maximum space of 64M bytes.

Only 44M (28M when CSM0=”0”) bytes is

addressable by chip selects.

Refer to FIGURE 7-1 for memory mapping of ST2202.

Control Register

Zero Page

User Memory

0000

007F

0080

00FF

User Memory /

Display Memory

0100

0200

01FF

3FFF

4000

Program Memory

(PRR)

16K bytes

7FFF

8000

Data Memory

(DRR)

32K bytes

FFFF

0000000~

0003FFF

0004000~

0007FFF

DRR = 000H

PRR = 001H

PRR = 000H

0008000~

000BFFF

000C000~

000FFFF

DRR = 001H

PRR = 003H

PRR = 002H

3FF0000~

3FF3FFF

3FF4000~

3FF7FFF

DRR = 7FEH

PRR = FFDH

PRR = FFCH

3FF8000~

3FFBFFF

3FFC000~

3FFFFFF

DRR = 7FFH

PRR = FFFH

PRR = FFEH

Interrupt Vector

7FE2

CPU Memory Mapping

Physical Memory Mapping

64M Bytes

Stack

Reserved

0FFF

1000

FIGURE 7-1 Memory Mapping

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