ST2202 datasheet(35/65 Pages) ETC

35 / 65 page

Sitronix

ST2202

Ver 2.0a

35/65

2003-May-05

5.. P

M D

A built-in PWM DAC is for analog sampling data or voice

signals. The structure of DAC is shown in TABLE 15-1.

There is an interrupt signal from DAC to CPU whenever

DAC data update is needed and the same signal will decide

the sampling rate of voice. In DAC mode, the frequency of

RC oscillator can’t less 2M Hz.

TABLE 15-1 Summary Of DAC Registers

Address Name R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$012

PSG1L

PSG1[7] PSG1[6] PSG1[5] PSG1[4] PSG1[3] PSG1[2] PSG1[1] PSG1[0]

0000 0000

$013

PSG1H

PSG1[11] PSG1[10] PSG1[9] PSG1[8]

- - - - 0000

$014

DAC

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

0000 0000

$016

PSGC

PCK[2]

PCK[1]

PCK[0]

DMD[1]

DMD[0]

INH

DACE=1

-000 0000

TABLE 15-2 DAC Data Register (DAC)

Address Name R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$014

DAC

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

0000 0000

Bit 7~0:

DAC[7~0] : DAC output data

Note: For Single-Pin Single Ended mode, the effective output resolution is 7 bit.

TABLE 15-3 DAC Control Register (PSGC)

Address Name R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$016

PSGC

PCK[2]

PCK[1]

PCK[0]

DMD[1]

DMD[0]

INH

DACE=1

- 000 0000

Bit 0:

DACE : PSG play as Tone (Noise) or DAC Generator selection bit

1 = PSG is used as DAC Generator

0 = PSG is used as Tone (Noise) Generator

Bit 1:

INH : DAC output inhibit control bit

1 = DAC output inhibit

0 = DAC output enable

Bit 3~2: DMD[1~0] : DAC output mode selection

00 = Single-Pin mode

: 7 bit resolution

01 = Two-Pin Two Ended mode

: 8 bit resolution

10 = Reserved

11 = Two-Pin Push Pull mode

: 8 bit resolution

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