AD9174 datasheet(37/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 37 of 164

DAC PLL CLOCK

÷4

PCLK

GENERATOR

CDR HALF

RATE CLOCKS

SERDES PLL

WITH INTERNAL VCO

LANE RATES

3Gbps TO 15.4Gbps

JESD204B MODE (REGISTER 0x110, BITS[4:0])

DATAPATH INTERPOLATION (REGISTER 0x111, BITS[7:4])

CHANNEL INTERPOLATION (REGISTER 0x111, BITS[3:0])

DIRECT DAC CLOCK

Figure 55. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

The reference clock to the SERDES PLL is always running at a

frequency, fREF, that is equal to 1/40 of the lane rate (PCLK rate).

For more information about the SERDES circuitry setup and

relevant register writes, see the Start-Up Sequence section. The

SERDES PLL block automatically tunes to the appropriate divider

range for the lane rate based on the SERDES mode being used. It

takes the DAC clock generated by either the DAC PLL, if in use, or

from the direct clock being sourced at the CLKIN± pins, divides

the DAC clock frequency by 4, and uses the JESD204B parameters

corresponding to the mode and interpolation values programmed

in Register 0x110 and Register 0x111 to determine the proper

dividers for generating the PCLK frequency (lane rate ÷ 40), as

shown in Figure 55.

Confirm that the SERDES PLL is working by reading

has locked.

Clock and Data Recovery

The deserializer is equipped with a CDR circuit. Instead of

recovering the clock from the JESD204B serial lanes, the CDR

recovers the clocks from the SERDES PLL. The SERDES PLL in

turn uses the PCLK as its reference, where the PCLK is derived

from the DAC clock. It is thus critical to lock the JESD204B

transmitter clock to the device clock of the AD9174.

The CDR circuit synchronizes the phase used to sample the data on

each serial lane independently. This independent phase adjustment

per serial interface ensures accurate data sampling and eases the

implementation of multiple serial interfaces on a PCB.

Power-Down Unused PHYs

Any unused physical and enabled lanes consume extra power

unnecessarily. Each lane that is not being used (SERDINx±) must

be powered off by writing a 1 to the corresponding bit of PHY_PD

(Register 0x201).

Equalization

To compensate for signal integrity distortions for each PHY

channel due to PCB trace length and impedance, the AD9174

employs an easy to use, low power equalizer on each JESD204B

channel. The AD9174 equalizers operating at the maximum lane

rate of 15.4 Gbps can compensate for up to 16 dB of insertion loss.

This equalizer performance is shown in Figure 56 for 15.4 Gbps,

near the maximum baud rate for the AD9174. The channel must

also meet the insertion loss deviation (also known as spectral

ripple) requirement of the JESD204B specification (less than

1.5 dB from 50 MHz to 0.75 times the baud rate).

FREQUENCY (GHz)

7.5

11.25

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–22

–24

3.75

EXAMPLE OF JESD204B

COMPLIANT CHANNEL

MINIMUM

ALLOWED CHANNEL

LOSS (JESD204B SPEC)

EXAMPLE OF AD9174

COMPATIBLE CHANNEL

MINIMUM ALLOWED

CHANNEL LOSS

AD9174

Figure 56. Insertion Loss Allowed

To ensure the AD9174 compensates for the amount of insertion

loss in the system, set the equalizer block appropriately. Table 22

shows the settings for the equalizer boost, equalizer gain, and

feedback controls, depending on the level of insertion loss in

the system. The equalizer boost setting is programmed for each

PHY lane (2-bit control for each) being used in Register 0x240

and Register 0x241. Similarly, the equalizer gain settings are

programmed for each PHY lane (2-bit control for each) used in

programmed per PHY lane (5-bit control for each, one control

per register) in Register 0x244 to Register 0x24B.

Table 22. Equalizer Register Control Settings per PHY Control

Insertion Loss

≤11 dB

>11 dB

Equalizer Boost

0x02

0x03

Equalizer Gain

0x01

0x03

Feedback

0x1F

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