AD9174 datasheet(99/164 Pages) AD

99 / 164 page

Data Sheet

AD9174

Rev. A | Page 99 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x03B

ROTATION_MODE

SYNCLOGIC_EN

This bit must always be set to 1 (default) for

both Subclass 0 and Subclass 1 operations.

0x1

R/W

RESERVED

Reserved. For proper operation, write this

bit to a 1.

0x0

R/W

PERIODIC_RST_EN

Synchronization required setting. Always

set this bit to 1 for both Subclass 0 and

Subclass 1 operation.

0x1

R/W

NCORST_AFTER_

ROT_EN

Set this bit to 1 to reset all NCOs after digital

reset or synchronization rotation. Either this

control or the START_NCO_SYNC bit

(Register 0x1E7, Bit 0) can be used to reset

all the NCOs (main and channel

datapaths).

0x1

R/W

[3:2]

RESERVED

Reserved.

0x0

[1:0]

ROTATION_MODE

Selects the circuitry to be reset when a

synchronization rotation occurs. Certain

bits being set to 1 determine the actions

taken when a synchronization rotation is

performed. Bit 0 corresponds to a SERDES

clock reset and realignment. Bit 1 corres-

ponds to a datapath soft off/on gain, which

must only be used if PA protection is in use. If

PA protection is not used, set Bit 1 to 0.

0x0

R/W

No action, with either the SERDES clocks or

the datapath, occurs when a synchro-

nization rotation occurs.

The links drop and the SERDES clocks are

reset. It is recommended to set this bit high

so that when a synchronization rotation is

performed, the SERDES clocks realign

properly.

The datapath automatically uses the soft

on/off functionality to turn on and off the

datapath stream during a synchronization

rotation to avoid corrupted data from

being transmitted. Only use this feature if

the PA protection block is in use.

Both the SERDES clock reset and datapath

soft on/off feature are enabled.

0x03F

TX_ENABLE

[7:6]

RESERVED

Reserved.

0x0

R/W

TXEN_DATAPATH_

DAC1

Selects whether the datapath of DAC1 is

muted when the TXEN1 pin is brought low.

0x0

R/W

Datapath output is normal.

If TXEN1 = 0, the datapath output is

immediately zeroed. If TXEN1 = 1, the

datapath outputs normal operation.

TXEN_DATAPATH_

DAC0

Selects whether the datapath of DAC0 is

muted when the TXEN0 pin is brought low.

0x0

R/W

Datapath output is normal.

If TXEN0 = 0, the datapath output is

immediately zeroed. If TXEN0 = 1, the

datapath outputs normal operation.

[3:0]

RESERVED

Reserved.

0x0

R/W

0x050

CAL_CLK_DIV

[7:4]

RESERVED

Reserved

0x2

R/W

[3:0]

CAL_CLK_DIV

Calibration register control. Set these bits

to 0xA for optimized calibration setting.

0x8

R/W

AD9174 Datasheet(PDF) 99 Page - Analog Devices

AD9174 Datasheet(HTML) 99 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL