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AD9174 Datasheet(PDF) 74 Page - Analog Devices |
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AD9174 Datasheet(HTML) 74 Page - Analog Devices |
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74 / 164 page  AD9174 Data Sheet Rev. A | Page 74 of 164 SYNCOUT±, SYSREF±, and CLK± Signals The SYSREF± signal on the AD9174 is a low speed, LVDS, differential signal. The SYNCOUTx± signals are LVDS or CMOS selectable. When LVDS mode is selected, use controlled impedance traces routed as 100 Ω differential impedance and 50 Ω to ground when routing these signals. As with the SERDIN0± to SERDIN7± data pairs, it is important to keep these signals separated from potential noise sources, such as high speed digital signals and noisy supplies. Separate the SYNCOUTx± signal from other noisy signals because noise on the SYNCOUTx± may be interpreted as a request for /K/ characters. It is important to keep similar trace lengths for the CLK± and SYSREF± signals from the clock source to each of the devices on either end of the JESD204B links (see Figure 97). If using a clock chip that can tightly control the phase of CLK± and SYSREF±, the trace length matching requirements are greatly reduced. CLOCK SOURCE ( AD9516-1, ADCLK925) LANE 0 LANE 1 LANE N – 1 LANE N DEVICE CLOCK DEVICE CLOCK SYSREF± SYSREF± SYSREF± TRACE LENGTH SYSREF± TRACE LENGTH DEVICE CLOCK TRACE LENGTH DEVICE CLOCK TRACE LENGTH Tx DEVICE Rx DEVICE Figure 97. SYSREF± Signal and Device Clock Trace Length |
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