AD9174 datasheet(44/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 44 of 164

FRAME CLOCK

LMFC

PCLK

DATA

DATA AT Tx FRAMER

ILAS

LMFCRX

TOTAL FIXED LATENCY = 30 PCLK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT

ILAS

TOTAL VARIABLE

LATENCY = 4

PCLK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

Figure 66. LMFC Delay Calculation Example

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9174 can read back

the link latency between LMFCRX for each link (with the

LMFCDel setting subtracted out) and the SYSREF± aligned

LMFC. This information is then used to calculate LMFCVar

and LMFCDel.

Figure 68 shows how DYN_LINK_LATENCY_0 (Register 0x302)

provides a readback showing the delay (in PCLK cycles) between

LMFCRX minus the LMFC_DELAY_x (fixed delay) setting set in

the SPI at that time and the transition from the ILAS to the first

data sample. By repeatedly power cycling and taking this measure-

ment, the minimum and maximum delays across power cycles

can be determined and used to calculate LMFCVar and

LMFCDel.

In Figure 68, for Link A, Link B, and Link C, the system

containing the AD9174 (including the transmitter) is power

cycled and configured 20 times. The AD9174 is configured as

described in the Sync Procedure section. Because the purpose

of this exercise is to determine LMFCDel and LMFCVar, the

LMFCDel value is programmed to 0 and the DYN_LINK_

LATENCY_0 value is read from Register 0x302. The variation

in the link latency over the 20 runs is shown in Figure 68,

described as follows:



Link A gives readbacks of 6, 7, 0, and 1. The set of recorded

delay values rolls over the edge of a multiframe at the

boundary of K/PCLK factor = 8. Add the number of PCLK

cycles per multiframe = 8 to the readback values of 0 and 1

because they rolled over the edge of the multiframe. Delay

values range from 6 to 9.



Link B gives delay values from 5 to 7.



Link C gives delay values from 4 to 7.

The example shown in Figure 68 is demonstrated in the following

steps. This example is in Subclass 1 to achieve deterministic

latency, and the example uses the case for F = 1. Therefore, the

number of PCLK cycles per multiframe = 8.

Calculate the minimum of all delay measurements across

all power cycles, links, and devices as follows:

MinDelay = min(all Delay values) = 4

Calculate the maximum of all delay measurements across

all power cycles, links, and devices as follows:

MaxDelay = max(all Delay values) = 9

Set LFMCVar to the maximum of 12 PCLK cycles. If

latency is required to be minimized for a given application,

calculate the total delay variation (with 2 PCLK cycles of

guard band on each end) across all power cycles, links, and

devices as follows:

LMFCVar = (MaxDelay + 2) − (MinDelay − 2)

= (9 + 2) − (4 − 2) = 11 − 2 = 9 PCLK cycles

Calculate the minimum delay in PCLK cycles (with

2 PCLK cycles of guard band) across all power cycles, links,

and devices as follows:

LMFCDel

= (MinDelay – 2) % (PCLKsperMF)

= (4 − 2) % 8

= 2 % 8 = 2 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the system.

Write LMFCVar to Register 0x306 for all devices in the system.

AD9174 Datasheet(PDF) 44 Page - Analog Devices

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