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Data Sheet

AD9174

Rev. A | Page 69 of 164

DAC On-Chip PLL

The AD9174 includes an integer PLL/VCO block that allows

generating a DAC clock (fDAC) from an external reference frequency

(fREF) between 25 MHz and 3080 MHz, applied to the CLKIN±

pins (see Figure 90). When using the on-chip PLL, select the

predivider (M) via Register 0x793, Bits[1:0] to internally divide

the reference frequency to be within the range of 25 MHz to

770 MHz of the phase frequency detector (PFD) circuitry block

input. Enable the DAC PLL synthesizer by setting Register 0x095,

Bit 0 to 0.

The internal VCO operates over a frequency range of 8.74 GHz

to 12.4 GHz, with additional divider settings if a lower DACCLK is

required by the application. The DAC clock rate is user

configurable to be the VCO frequency (8.74 GHz to 12.4 GHz),

the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the

VCO frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting

instructions on how to program the PLL.

To generate the required VCO control voltage from the charge

pump (CP) output, the AD9174 DAC PLL requires an external

loop filter. The recommended filter is a passive low-pass filter of

a topology similar to the one shown in Figure 90. Generally, the

pass band width of the filter (bandwidth) trades off loop response

time during a frequency change with loop stability after the

initial frequency lock occurs. For proper filter layout and

component selection, which results in optimal performance for

most applications, refer to the documentation of the AD9174-

FMC-EBZ evaluation board. The user may however customize

the filter to fit a specific application, according to the PFD

frequency, reference clock phase noise, and DAC output phase

noise requirements. For example, to lower DACCLK jitter when

using the PLL, a higher PFD frequency minimizes the contribution

of in band noise from the PLL. Set the PLL filter bandwidth

such that the in band noise of the PLL intersects with the open-

loop noise of the VCO to minimize the contributions of both

blocks to the overall noise.

The best jitter performance is typically achieved when using an

external, high performance clock source.

The DAC PLL uses an integer type synthesizer to generate the

DACCLK for both DAC0 and DAC1, implying that the

generated DACCLK must be an integer multiple of the input

reference clock. The relationship between DAC clock and the

reference clock is as follows:

fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1)

where:

fDAC is the desired DAC clock rate.

N is the VCO feedback divider ratio, ranging from 2 to 50.

fREF is the reference clock.

M is the reference clock divider ratio. The valid values for

reference clock divider (predivider) are 1, 2, 3, or 4 by setting

The VCO automatic calibration is triggered by the falling edge

of Register 0x792, Bit 1 transitioning from a logic high to logic

low. A lock detector bit (Register 0x7B5, Bit 0) is provided to

indicate that the DAC PLL achieved lock. If Register 0x7B5,

Bit 0 = 1, the PLL has locked.

PFD

CHARGE

PUMP

VCO

÷N

÷8

÷M

CLK

RCVR

÷2

÷L

CLKIN+

CLKIN–

CLK

DRIVER

CLKOUT+

DACCLK

N = 2 TO 50

M = 1, 2, 3, 4

PCB

OFF-CHIP FILTER

FILT_COARSE

REG 0x094, BITS[1:0]

REG 0x095, BIT 0

REG 0x799, BITS[5:0]

REG 0x799, BITS[7:6]

L = 1, 2, 3, 4

FILT_VCM

FILT_FINE

÷3

DAC

REG 0x793, BITS[1:0]

Figure 90. DAC PLL and Clock Path Block Diagram

AD9174 Datasheet(PDF) 69 Page - Analog Devices

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