AD9174 datasheet(38/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 38 of 164

Figure 57 and Figure 58 are provided as points of reference for

hardware designers and show the insertion loss for various

lengths of well laid out stripline and microstrip transmission

lines, respectively. See the Hardware Considerations section for

specific layout recommendations for the JESD204B channel.

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (GHz)

STRIPLINE = 6"

STRIPLINE = 10"

STRIPLINE = 15"

STRIPLINE = 20"

STRIPLINE = 25"

STRIPLINE = 30"

Figure 57. Insertion Loss of 50 Ω Striplines on FR4

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (GHz)

6" MICROSTRIP

10" MICROSTRIP

15" MICROSTRIP

20" MICROSTRIP

25" MICROSTRIP

30" MICROSTRIP

Figure 58. Insertion Loss of 50 Ω Microstrips on FR4

DATA LINK LAYER

The data link layer of the AD9174 JESD204B interface accepts

the deserialized data from the PHYs and deframes and descrambles

the data so that data octets are presented to the transport layer

to be recombined into the original data samples ahead of the

DAC core. The architecture of the data link layer is shown in

Figure 59. The data link layer consists of a synchronization

FIFO for each lane, a crossbar switch, a deframer, and a

descrambler.

The AD9174 can be set up to receive data from either a single-

link or dual-link high speed JESD204B serial data interface.

When operating in dual-link mode, the data link layer abstracts

the interface to appear as two independent JESD204B links to

the user, each occupying a maximum of four lanes. In either

mode, all eight lanes of the JESD204B interface handle link

layer communications such as code group synchronization

(CGS), frame alignment, and frame synchronization.

The AD9174 decodes 8-bit/10-bit control characters, which

mark the edges of the frame and help maintain alignment

between serial lanes. Each AD9174 serial interface link can issue

a synchronization request by setting its SYNCOUTx± signals

low. The synchronization protocol follows Section 4.9 of the

JESD204B standard. When a stream of four consecutive /K/

symbols is received, the AD9174 deactivates the synchronization

request by setting the SYNCOUTx± signals high at the next

internal LMFC rising edge. Then, the AD9174 waits for the

transmitter to issue an initial lane alignment sequence (ILAS).

During the ILAS, all lanes are aligned using the /A/ to /R/

character transition as described in theJESD204B Serial Link

Establishment section. Elastic buffers hold early arriving lane

data until the alignment character of the latest lane arrives. At

this point, the buffers for all lanes are released and all lanes are

aligned (see Figure 60).

LANE 0 DESERIALIZED

AND DESCRAMBLED DATA

LANE 0 DATA CLOCK

SERDIN0±

FIFO

SERDIN7±

FIFO

CROSS-

BAR

SWITCH

LANE 7 DESERIALIZED

AND DESCRAMBLED DATA

LANE 7 DATA CLOCK

PCLK

DATA LINK LAYER

SPI CONTROL

SYSREF±

SYNCOUTx±

SYSTEM CLOCK

PHASE DETECT

LANE 0 OCTETS

LANE 7 OCTETS

QUAD-BYTE

DEFRAMER

QBD

Figure 59. Data Link Layer Block Diagram

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