AD9174 datasheet(100/164 Pages) AD

100 / 164 page

AD9174

Data Sheet

Rev. A | Page 100 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x051

CAL_CTRL

CAL_CTRL0

Calibration setting. Set this bit to 1.

0x1

R/W

Reset the calibration engine.

Enable the calibration routine.

[6:3]

RESERVED

Reserved.

0x0

R/W

[2:1]

CAL_CTRL1

Calibration mode selection. Set this bit

field to 1 for optimized calibration mode.

Paged by the MAINDAC_PAGE bits in

0x1

R/W

Set calibration control setting.

CAL_START

Start calibration. After starting calibration, do

not write to any register from Register 0x051

to Register 0x061 until Register 0x052, Bit

2 reads low (indicating that the calibration

is no longer active). Paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0

R/W

0x052

CAL_STAT

[7:3]

RESERVED

Reserved.

0x0

R/W

CAL_ACTIVE

Calibration active status flag. A readback

of 1 indicates the calibration routine is still

in progress. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0

CAL_FAIL_SEARCH

Calibration failure flag. A readback of 1

indicates the calibration routine failed and is

possibly not valid. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0

CAL_FINISH

Calibration complete flag. A readback of 1

indicates the calibration completed. This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0

0x05A

FSC1

[7:0]

FSC_CTRL[7:0]

Sets the full-scale (maximum) current that

is available from the DACx analog outputs.

This control is paged by the MAINDAC_

PAGE bits in Register 0x008. Full-scale

current = 15.625 mA + FSC_CTRL ×

(25/256) (mA).

0x28

R/W

0x061

CAL_DEBUG0

RESERVED

Reserved.

0x0

R/W

CAL_CTRL2

Calibration control. Set this bit to 1 for

optimized calibration setting.

0x1

R/W

CAL_CTRL3

Calibration control. Set this bit to 1 for

optimized calibration setting.

0x1

R/W

RESERVED

Reserved.

0x0

R/W

CAL_CTRL4

Calibration control. Set this bit to 1 for

optimized calibration setting.

0x0

R/W

[2:0]

RESERVED

Reserved.

0x0

R/W

0x081

CLK_CTRL

[7:2]

RESERVED

Reserved.

0x0

R/W

CAL_CLK_PD1

After the calibration is complete for DAC1

(Register 0x052, Bit 0 = 1), set this bit high

to power down the calibration clock.

0x0

R/W

CAL_CLK_PD0

After the calibration is complete for DAC0

(Register 0x052, Bit 0 = 1), set this bit high

to power down the calibration clock.

0x0

R/W

0x083

NVM_CTRL0

NVM_CTRL0A

NVM register control for the ring oscillator.

0x0

R/W

[6:2]

RESERVED

Reserved.

0x0

[1:0]

NVM_CTRL0B

NVM register control for the ring oscillator.

0x2

R/W

Divide by 8.

Divide by 16.

Divide by 32.

Divide by 64.

AD9174 Datasheet(PDF) 100 Page - Analog Devices

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