Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AD9174 Datasheet(PDF) 9 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 9 Page - Analog Devices

Back Button AD9174 Datasheet HTML 5Page - Analog Devices AD9174 Datasheet HTML 6Page - Analog Devices AD9174 Datasheet HTML 7Page - Analog Devices AD9174 Datasheet HTML 8Page - Analog Devices AD9174 Datasheet HTML 9Page - Analog Devices AD9174 Datasheet HTML 10Page - Analog Devices AD9174 Datasheet HTML 11Page - Analog Devices AD9174 Datasheet HTML 12Page - Analog Devices AD9174 Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 164 page
background image
Data Sheet
AD9174
Rev. A | Page 9 of 164
SERIAL PORT AND CMOS PIN SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 5.
Parameter
Symbol
Test Comments/Conditions
Min
Typ
Max
Unit
WRITE OPERATION
See Figure 51
Maximum SCLK Clock Rate
fSCLK, 1/tSCLK
80
MHz
SCLK Clock High
tPWH
SCLK = 20 MHz
5.03
ns
SCLK Clock Low
tPWL
SCLK = 20 MHz
1.6
ns
SDIO to SCLK Setup Time
tDS
1.154
ns
SCLK to SDIO Hold Time
tDH
0.577
ns
CS to SCLK Setup Time
tS
1.036
ns
SCLK to CS Hold Time
tH
−5.3
ps
READ OPERATION
See Figure 50
SCLK Clock Rate
fSCLK, 1/tSCLK
48.58
MHz
SCLK Clock High
tPWH
5.03
ns
SCLK Clock Low
tPWL
1.6
ns
SDIO to SCLK Setup Time
tDS
1.158
ns
SCLK to SDIO Hold Time
tDH
0.537
ns
CS to SCLK Setup Time
tS
1.036
ns
SCLK to SDIO Data Valid Time
tDV
9.6
ns
SCLK to SDO Data Valid Time
tDV
13.7
ns
CS to SDIO Output Valid to High-Z
Not shown in Figure 50 or
Figure 51
5.4
ns
CS to SDO Output Valid to High-Z
Not shown in Figure 50 or
Figure 51
9.59
ns
INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1)
Voltage Input
High
VIH
1.48
V
Low
VIL
0.425
V
Current Input
High
IIH
±100
nA
Low
IIL
±100
nA
OUTPUTS (SDIO, SDO)
Voltage Output
High
VOH
0 mA load
1.69
V
4 mA load
1.52
V
Low
VOL
0 mA load
0.045
V
4 mA load
0.175
V
Current Output
High
IOH
4
mA
Low
IOL
4
mA
INTERRUPT OUTPUTS (IRQ0, IRQ1)
Voltage Output
High
VOH
1.71
V
Low
VOL
0.075
V



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com