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AD9174 Datasheet(PDF) 45 Page - Analog Devices |
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AD9174 Datasheet(HTML) 45 Page - Analog Devices |
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45 / 164 page ![]() Data Sheet AD9174 Rev. A | Page 45 of 164 ILAS DATA SYSREF± ALIGNED DATA LMFCRX DYN_LINK_LATENCY_x Figure 67. DYN_LINK_LATENCY_x Illustration 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 DYN_LINK_LATENCY_x ALIGNED DATA (LINK A) DETERMINISTICALLY DELAYED DATA LMFCRX ALIGNED DATA (LINK B) ALIGNED DATA (LINK C) FRAME CLOCK LMFC PCLK DATA ILAS DATA ILAS DATA ILAS DATA ILAS LMFC_DELAY = 6 (FRAME CLOCK CYCLES) LMFC_VAR = 7 (PCLK CYCLES) Figure 68. Multilink Synchronization Settings, Derived Method Example DELAY BUFFER 1 DELAY BUFFER 0 F2S_0 F2S_1 DAC A_I0[15:0] DAC A_Q0[15:0] PCLK_1 LANE 0 OCTETS LANE 7 OCTETS PCLK_0 SPI CONTROL LANE 3 OCTETS LANE 4 OCTETS DAC B_I0[15:0] DAC B_Q0[15:0] TRANSPORT LAYER (QBD) SPI CONTROL PCLK_0 TO PCLK_1 FIFO Figure 69. Transport Layer Block Diagram |
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