AD9174 datasheet(68/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 68 of 164

ANALOG INTERFACE

DAC INPUT CLOCK CONFIGURATIONS

The AD9174 DAC sample clock or device clock (DACCLK) can

be received directly through CLKIN± (Pin H12 and Pin J12) or

generated using an integer PLL/VCO, integrated on-chip, with the

reference clock provided through the same CLKIN± differential

input pins. The DACCLK serves as a reference for all the clock

domains within the AD9174.

The AD9174 uses a low jitter, differential clock receiver that is

capable of interfacing directly to a differential or single-ended

clock source. Because the input is self biased, with a nominal

impedance of 100 Ω, it is recommended that the clock source be

ac-coupled to the CLKIN± input pins. Phase noise performance

can be improved with higher clock input levels (larger swing,

resulting in higher effective slew rate), up to the recommended

maximum limits. Because the DACCLK is the sampling clock

for data within the analog cores (DACx), the quality of the clock

signal at the AD9174 clock input pins is paramount and directly

impacts the analog ac performance of the DAC. Select a clock

source with phase noise and spur characteristics that meet the

target application requirements. Generally, the use of a

PLL/VCO or other clock multipliers, internal or external to the

DAC, also multiplies the resulting phase noise (jitter). The best

phase noise performance is typically achieved using an external

clock running at the desired DAC clock rate, with the PLL/VCO

bypassed.

In cases where low phase noise is not a critical requirement, the

PLL/VCO provides a convenient way to operate the AD9174 at

DAC clock rates as high as 12.4 GHz without the need for

complex, multigigahertz clocking solutions, The PLL reference

frequency at CLKIN± can be typically orders of magnitude

lower than the operating DACCLK rate. The PLL then generates

a control voltage for a downstream VCO, which in effect

multiplies the reference clock up to the desired DACCLK

frequency.

The typical phase noise performance when the AD9174 is directly

clocked and the input clock duty cycle correction is on (enabled by

default) is shown in Figure 88, compared with the phase noise due

to the on-chip PLL/VCO.

–180

–160

–140

–120

–100

–80

–60

–40

–20

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

PLL OFF (DIRECT CLOCK)

PLL ON (PFD = 491.52MHz)

Figure 88. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase

Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency

50Ω

CLK+

CLK–

170kΩ

PLL/VCO

DCC0

DCC1

DAC1

DAC0

–

OPTIMIZED INPUT

BIAS

CLOCK/

PLL MUX

CLOCK/

PLL MUX

Figure 89. Clock Receiver Input Simplified Equivalent Circuit

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