AD9174 datasheet(70/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 70 of 164

CLOCK OUTPUT DRIVER

The AD9174 is capable of generating a high quality, divided

down version of the DACCLK, which can be used to clock critical

system components, such as a companion ADC. The integer

clock divider supports divide ratios of 1, 2, 3, and 4 and can be

programmed by Register 0x799, Bits[7:6] to set the desired

output frequency. The 3 db bandwidth of the clock driver is

between 727.5 MHz and 3 GHz, although frequencies outside

this range can be generated with some penalty to both power

and spurious performance at the clock output.

The clock driver does not have an impact on the performance

of the DACx analog outputs.

ANALOG OUTPUTS

The AD9174 provides two fully independent DAC cores, DAC0

and DAC1, each with a differential output. Figure 91 shows an

equivalent output circuit for a single DAC core. Each output is

internally terminated with a 100 Ω resistor (RINT) that eliminates

the need to resistively terminate the DAC output externally on

the PCB. To properly dc bias the output stage, two RF chokes,

one for each output branch, are required to provide a dc current

path for the standing current of each DACx output. The

inductance value of the choke depends on the desired output

frequency range. In general, a larger choke provides a lower

cutoff output frequency.

Due to parasitic capacitances and inductances at the output, a

constant 100 Ω termination impedance cannot be easily

maintained across the full operating frequency range of the

AD9174, which can be anywhere between dc and >6 GHz,

depending on the application. The output impedance of each

DAC can be determined through measurement. Generally,

when matching the DAC output to a typical single-ended 50 Ω

load, a 2:1 balun is recommended when operating below ~2 GHz.

A 1:1 balun is recommended when operating above ~2 GHz,

which also extends the 3 dB roll-off of the output beyond 4 GHz

with proper PCB layout techniques.

DAC Full-Scale Power

IOUTFS is the full-scale current output at the positive and negative

branch of the DACx output, denoted as IP and IN in Figure 91 to

Figure 93. The default full-scale current is set to 19.531 mA,

although it can be adjusted from 15.625 mA to 25.977 mA by

programming the appropriate value in Register 0x05A.

IOUTFS = 15.625 mA + FSC_CTRL × (25/256) (mA)

As shown in Figure 91 to Figure 93, the amount of power delivered

to an external load depends on multiple factors, such as the IOUTFS

setting, the internal impedance of the DAC, and the external

loading and parasitic inductances and capacitances that the PCB

and other components present at the output. The true power that

can be delivered to a load is determined by measurements.

Alternatively, the DAC output power can be estimated from the

DAC equivalent model, by making certain assumptions about

the parasitic loading presented by a particular PCB design. The

DAC output can be modeled as a pair of dc current sources that

continuously provide dc, set to IOUTFS/2, summed with a parallel

ac source set by the incoming data samples, namely DACCODE,

that are sampled to the analog output at the rate of DACCLK.

Together, the three current sources model the output switch

network internal to each analog output, which define the

instantaneous current out of the positive and negative branches

of each differential output (IP and IN, respectively).

Assuming that parasitic capacitances and inductances are

negligible (which may not always be the case, especially at

output frequencies above ~2 GHz), the output current

presented to the load can be calculated as follows:

IP = (DACCODE + 2N − 1) × ILSB

IN = ((2N −1 – 1) – DACCODE) × ILSB

and,

ILOAD = (IP – IN) × RINT/(RINT + RLOAD)

where,

ILSB = IOUTFS/2N

DACCODE is a sample value between −2N − 1 and 2N – 1 − 1 (as a

signed decimal representation of twos complement data).

For a single-tone output (pure sinewave), the rms power

delivered to the load can be calculated as follows:

ILOAD(RMS) = ILOAD_MAX/√2

where ILOAD_MAX is the maximum load current delivered at the

maximum DACCODE, as calculated previously, and,

PLOAD (W) = (ILOAD(RMS))2 × RLOAD

PLOAD (dBm) = 10 × log(PLOAD(W))

MSB Shuffle

Depending on the analog signal level, some or all of the MSB

current sources from the DAC may be static (unused). Particularly

at lower signal levels, when most MSBs are static, any mismatch

errors specific to the few MSBs that are dynamic may appear as

a degradation to spurious performance at the analog outputs.

On average, spurious performance is improved when the active

MSBs are continuously remapped ( or shuffled) and randomly

selected from the total number of available MSBs before sampling

at the DACx analog outputs. MSB shuffle is a form of error

averaging. Because the cumulative errors are pseudorandom,

the improved SFDR comes at the expense of higher NSD.

Shuffling is only feasible when there are spare MSBs available

that are otherwise static, so that they can be randomly switched

in. Therefore, the benefit from shuffling is diminished as the

number of dynamic MSBs is increased, such as for signals that

experience frequent peaks near the full-scale current of the

DAC. With a sinusoidal output at full-scale, for example, the

benefit from MSB shuffling is largely nonexistent when

compared to performance with traditional (thermometer)

encoding.

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