AD9174 datasheet(59/164 Pages) AD

59 / 164 page

Data Sheet

AD9174

Rev. A | Page 59 of 164

When the calculated average power exceeds a specified

threshold, a trigger signal is issued. The registers to program the

thresholds for the long and short average filters, along with their

respective detected power calculation readbacks, are listed in

Table 42.

Table 42. PDP Threshold and Power Calculation Controls

Bits

Control

0x583

[7:0]

LONG_PA_THRESHOLD[7:0]

0x584

[4:0]

LONG_PA_THRESHOLD[12:8]

0x586

[7:0]

LONG_PA_POWER[7:0]

0x587

[4:0]

LONG_PA_POWER[12:8]

0x588

[7:0]

SHORT_PA_THRESHOLD[7:0]

0x589

[4:0]

SHORT_PA_THRESHOLD[12:8]

0x58B

[7:0]

SHORT_PA_POWER[7:0]

0x58C

[4:0]

SHORT_PA_POWER[12:8]

Main Datapath Interpolation

The interpolation options available within the main datapath

are bypass (1×), 2×, 4×, 6×, 8× and 12×. Each of the half-band

filters used for interpolation have up to 80% bandwidths with

85 dB of stop band rejection. The channel half-band cascaded

configuration is shown in Figure 78, with each of the useable

bandwidths of the interpolation filters listed in Table 43.

HB3

2×

HB4

2×

TB1

3×

HB5

2×

Figure 78. Main Datapath Interpolation Half-Band Filter Block Diagram

Table 43. Main Datapath Interpolation Useable Bandwidths

and Rejection

Half-Band Filter

Bandwidth

(×fIN_FILTER)

Stop Band Rejection (dB)

HB3

80%

HB4

40%

TB1

40%

HB5

20%

Main Datapath Digital Modulation

The main datapath 48-bit NCOs architecture is largely identical

to the channelizer NCOs that were described in earlier sections.

Their operation is similar as well. However, unlike the channelizer

NCOs, the main datapath NCOs operate at a higher clock rate,

the same rate as the analog DAC cores (fDAC), which allows the

NCOs to generate frequencies across a wider range. See the

48-Bit Integer/Modulus NCO section for more details

NCO mode is selected as shown in Table 44. These controls are

paged per the main DAC page masks, MAINDAC_PAGE

(Register 0x008, Bits[7:6]).

Table 44. Main Modulation Mode Selection

Modulation Mode

Modulation Type

Bit 3

Bit 2

None

0b0

48-Bit Integer NCO

0b1

0b0

48-Bit Dual Modulus NCO

0b1

The main NCO blocks also contain sideband selection controls

as well as options for how the FTW and phase offset controls

are updated.

The phase offset word control can be calculated as follows:

−180° ≤ Degrees Offset ≤ +180°

Degrees Offset = 180° × (DDSM_NCO_PHASE_OFFSET/215)

where DDSM_NCO_PHASE_OFFSET is a 16-bit twos complement

value programmed in the registers listed in Table 45.

Table 45. Main Datapath NCO Phase Offset Registers

Address

Value

Description

0x11C

DDSM_NCO_PHASE_OFFSET[7:0]

8 LSBs of phase offset

0x11D

DDSM_NCO_PHASE_OFFSET [15:8]

8 MSBs of phase offset

48-Bit Integer/Modulus NCO

The main datapath NCOs use a similar architecture to the

channelizer NCOs, as shown in Figure 74. Because the main

datapath NCOs are clocked at the same rate as fDAC, this

configuration allows output signals to be placed anywhere in

the output spectrum up to ±fDAC/2 with very fine frequency

resolution.

The NCO produces a quadrature carrier to translate the input

signal to a new carrier frequency, similar to the channelizer

NCOs. Refer to the corresponding channelizer NCO section for

more details.

The FTW for the main datapath NCOs is calculated in the same

manner as the FTW for the channelizer NCOs. An important

distinction is that the clock rate of the main datapath NCOs

(fNCO,CLK) is equal to the DAC sample rate (fDAC, 12.6 GSPS

maximum). Calculate fNCO,CLK using the following formula:

fNCO,CLK = fDAC = fDATA × Channel Interpolation × Main

Interpolation

The FTWs for each individual NCO can be programmed

separately and are calculated using the following formula:

− fNCO,CLK /2 ≤ fCARRIER < + fNCO,CLK /2

DDSM_FTW = (fCARRIER /fNCO,CLK) × 248

where:

fCARRIER is the output frequency of the NCO.

fNCO,CLK is the sampling clock frequency of the NCO.

DDSC_FTW is a 48-bit, twos complement number.

The frequency tuning word is set as shown in Table 46.

AD9174 Datasheet(PDF) 59 Page - Analog Devices

AD9174 Datasheet(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL