AD9174 datasheet(81/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 81 of 164

Crossbar mapping writes the SERDINx input pin that is the source for each given logical lane in these registers. A value of x corresponds

to mapping data from the SERDINx± pin to the logical lane of the control bit field. The values in Table 59 vary with different PCB layout

routing.

Table 59. Transport Layer Setup, Synchronization, and Enable Links

R/W

Bits

Value

Description

0x308

[7:0]

Crossbar setup. Program the physical lane value that is providing data (the source) for each of the

logical lanes. [5:3] = Logical Lane 1 source, [2:0] = Logical Lane 0 source.

0x309

[7:0]

[5:3] = Logical Lane 3 source, [2:0] = Logical Lane 2 source.

0x30A

[7:0]

[5:3] = Logical Lane 5 source, [2:0] = Logical Lane 4 source.

0x30B

[7:0]

[5:3] = Logical Lane 7 source, [2:0] = Logical Lane 6 source.

0x306

[7:0]

0x0C

If operating in Subclass 0, this register write is not needed.

0x307

[7:0]

0x0C

If operating in Subclass 0, this register write is not needed.

0x304

[7:0]

If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be

determined by following one of the deterministic latency methods (with or without known

delays), as mentioned in the Link Delay section.

0x305

[7:0]

If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be

determined by following one of the deterministic latency methods (with or without known

delays), as mentioned in the Link Delay section.

0x03B

[7:0]

0xF1

Enable the sync logic, and set the rotation mode to reset the synchronization logic upon a sync

reset trigger.

0x03A

[7:0]

0x02

Set up sync for one-shot sync mode.

SYSREF±

If operating in Subclass 1, send SYSREF± pulse edges to the device for synchronization alignment.

0x300

LINK_MODE

Corresponds to the mode selection made in Register 0x110.

0b0 = single-link mode.

0b1 = dual-link mode.

0b0

Select Link 0 for setup. This bit selects which link QBD is being paged.

0b0 = Link 0 (QBD0).

0b1 = Link 1 (QBD1).

[1:0]

LINK_EN

Enables the links.

0b01 = single-link mode

0b11 = dual-link mode.

Table 60. Cleanup Registers

R/W

Bits

Value

Description

0x085

[7:0]

0x13

Set to the default register value.

0x1DE

[7:0]

0x00

Disable analog SPI. To debug and continue readback capability, write 0x03.

0x008

[7:0]

0xC0

Page all main DACs for TXEN control update.

0x596

[7:0]

0x0C

SPI turn on TXENx feature.

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