AD9174 datasheet(47/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 47 of 164

Configuration Parameters

The AD9174 modes refer to the link configuration parameters

for L, K, M, N, NP, S, and F. Table 30 provides the description

and addresses for these settings.

Table 30. Configuration Parameters

JESD204B

Setting

Description

Address

L − 1

Number of lanes minus 1.

Bits[4:0]

F − 1

Number of ((octets per frame) per

lane) minus 1.

Bits[7:0]

K − 1

Number of frames per multiframe

minus 1.

Bits[4:0]

M − 1

Number of converters minus 1.

Bits[7:0]

N − 1

Converter bit resolution minus 1.

Bits[4:0]

NP − 1

Bit packing per sample minus 1.

Bits[4:0]

S − 1

Number of ((samples per

converter) per frame) minus 1.

Bits[4:0]

High density format. Set to 1.

Bit 7

DID

Device ID. Match the device ID

sent by the transmitter.

Bits[7:0]

BID

Bank ID. Match the bank ID sent by

the transmitter.

Bits[7:0]

LID0

Lane ID for Lane 0. Match the Lane

ID sent by the transmitter on

Logical Lane 0.

Bits[4:0]

JESDV

JESD204x version. Match the

version sent by the transmitter

(0x0 = JESD204A, 0x1 = JESD204B).

Bits[7:5]

The AD9174 truncates the output of the main digital datapath

to the value of N bits for the selected mode, which is then sent

to the DAC core. It is possible to send the value of NP number

of bits worth of data with the lower NP − N LSBs padded as 0s,

or to send the full NP number of bits data across the SERDES

lanes. In either case, the lower NP − N LSBs are truncated prior

to the DAC core.

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes are automatically

deskewed. All logical lanes are enabled or not based on the

number of lanes for the mode setting chosen in Register 0x110,

Bits[4:0]. The physical lanes are all powered up by default. To

disable power to physical lanes that are not being used, set Bit x

in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0

to enable it. The logical lanes must be enabled and deskewed on

a per link basis using the LINK_PAGE control (Register 0x300,

Bit 2). Set Bit x in Register 0x46C to 1 to deskew Link Logical

Lane x for the selected link page.

JESD204B TEST MODES

PRBS Testing

The JESD204B receiver on the AD9174 includes a PRBS pattern

checker on the back end of the PHY layer. The pattern checker

supports PRBS7, PRBS15, and PRBS31 data patterns, as defined

in the JESD204B specifications. The PRBS pattern can be sourced

from an external JESD204B transmitter, such a field-programmable

gate array (FPGA), or alternatively generated by the internal PRBS7

generator as described in the Internal PRBS7 Generator section.

This functionality allows testing of the bit error rate (BER) on

each physical lane of the AD9174 as well as the JESD204B PHY

as a whole. Low BER during PRBS testing confirms proper clocking

and clock synchronization, and confirms that the intercom-

nections (traces, connectors, and cabling) between the JESD204B

transmitter and receiver is of sufficient quality. Although the

PHY PRBS pattern checker does not require that the JESD204B

link be fully established, the JESD204B mode on the AD9174

must be configured so that the physical lanes are properly clocked

and are ready to receive PRBS data. The PRBS data must not be

8-bit/10-bit encoded. PRBS pattern verification can be performed

on multiple lanes at once or on one lane at a time. The error

count for each failing JESD204B lane is reported independently.

The process for enabling the PRBS checker on the AD9174 is as

follows:

1. Start sending a PRBS7, PRBS15, or PRBS31 looped pattern,

either from a JESD204B transmitter, or from the internal

PRBS7 generator of the AD9174.

2. Select the appropriate PRBS pattern to be received by

writing to Register 0x316, Bits[3:2], as shown in Table 31.

3. Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For example,

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

Any running JESD204B link is interrupted at this point.

4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0

to 1 then back to 0 to reset the status registers to the default

value.

5. Set PHY_PRBS_TEST_THRESHOLD_xBITS (Register 0x319

to Register 0x317, Bits[23:0]) as desired.

6. Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,

Bit 1). The rising edge of PHY_TEST_START starts the test.

a. In some cases, it may be necessary to repeat Step 4 at

this point. Toggle PHY_TEST_RESET (Register 0x316,

Bit 0) from 0 to 1, then back to 0.

7. Wait to accumulate the desired number of bits, or at least

500 ms.

8. Stop the test by writing PHY_TEST_START (Register 0x316,

Bit 1) = 0.

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