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AD9174 Datasheet(PDF) 98 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 98 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 98 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
MUX_PAERR1
If EN_PAERR1 is set, this control chooses
the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0x02B
IRQ_OUTPUT_MUX2
[7:6]
RESERVED
Reserved.
0x0
R
5
MUX_DLL_LOST
If EN_DLL_LOST is set, this control chooses
the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
4
MUX_DLL_LOCK
If EN_DLL_LOCK is set, this control chooses
the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
[3:2]
RESERVED
Reserved.
0x0
R/W
1
MUX_PLL_LOST
If EN_PLL_LOST is set, this control chooses
the
A
IRQxE
A
pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0
MUX_PLL_LOCK
If EN_PLL_LOCK is set, this control chooses
the
A
IRQxE
A
pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0x02C
IRQ_STATUS_ALL
[7:1]
RESERVED
Reserved.
0x0
R
0
IRQ_STATUS_ALL
This bit is an OR of all the bits in
Register 0x24 to Register 0x27. Writing a
one to this bit clears any latched
A
IRQxE
A
signals in Register 0x24 to Register 0x27.
0x0
R/W
0x036
SYSREF_COUNT
[7:0]
SYSREF_COUNT
Number of rising SYSREF± edges to ignore
before synchronization (pulse counting
mode).
0x0
R/W
0x039
SYSREF_ERR_
WINDOW
7
RESERVED
Reserved.
0x0
R
[6:0]
SYSREF_ERR_
WINDOW
Amount of jitter allowed on the SYSREF±
input. SYSREF± jitter variations larger than
this trigger an interrupt. Units are in DAC
clocks.
0x0
R/W
0x03A
SYSREF_MODE
[7:5]
RESERVED
Reserved.
0x0
R
4
SYNC_ROTATION_
DONE
Synchronization logic rotation complete flag.
0x1
R
[3:2]
RESERVED
Reserved.
0x0
R
1
SYSREF_MODE_
ONESHOT
Enable one-shot synchronization rotation
mode.
0x0
R/W
00
Monitor mode. Status/error flag for IRQ_
SYSREF_JITTER is 1 if the SYSREF± edge is
outside the error window (Register 0x039,
Bits[6:0]).
01
Perform a single synchronization on the next
SYSREF±, then switch to monitor mode.
0
RESERVED
Reserved.
0x0
R/W



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