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AD9174 Datasheet(PDF) 80 Page - Analog Devices |
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AD9174 Datasheet(HTML) 80 Page - Analog Devices |
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80 / 164 page  AD9174 Data Sheet Rev. A | Page 80 of 164 Table 58. JESD204B SERDES Required Interface Setup R/W Register Bits Value Description W 0x240 [7:0] 0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0xAA; otherwise, set to 0xFF. W 0x241 [7:0] 0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0xAA; otherwise, set to 0xFF. W 0x242 [7:0] 0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0x55; otherwise, set to 0xFF. W 0x243 [7:0] 0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0x55; otherwise, set to 0xFF. W 0x244 [7:0] 0x1F EQ settings. W 0x245 [7:0] 0x1F EQ settings. W 0x246 [7:0] 0x1F EQ settings. W 0x247 [7:0] 0x1F EQ settings. W 0x248 [7:0] 0x1F EQ settings. W 0x249 [7:0] 0x1F EQ settings. W 0x24A [7:0] 0x1F EQ settings. W 0x24B [7:0] 0x1F EQ settings. W 0x201 [7:0] Power down unused PHYs. Bit x corresponds to SERDINx± pin power-down. W 0x203 If in single-link mode, set to 0x01. If in dual-link mode and using both SYNCOUTx± signals, set to 0x00. 1 0b0 Power up SYNCOUT0± driver by setting this bit to 0. 0 Power up SYNCOUT1± driver by setting this bit to 0 if using dual link and both SYNCOUTx± signals. W 0x253 [7:0] 0x01 Set SYNCOUT0± to be LVDS output. For CMOS output on SYNCOUT0+, set Bit 0 to 0. W 0x254 [7:0] 0x01 Set SYNCOUT1± to be LVDS output. For CMOS output on SYNCOUT1+, set Bit 0 to 0. W 0x210 [7:0] 0x16 SERDES required register write. W 0x216 [7:0] 0x05 SERDES required register write. W 0x212 [7:0] 0xFF SERDES required register write. W 0x212 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x11 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x200 [7:0] 0x00 Power up the SERDES circuitry blocks. Pause Wait 100 ms. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x40 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x00 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x280 [7:0] 0x05 SERDES required register write. W 0x280 [7:0] 0x01 Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration. R 0x281 0 0b1 Ensure Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked. |
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