AD9174 datasheet(63/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 63 of 164

MODULATOR SWITCH

For added flexibility, the final NCO block (NCO0 and NCO1, to

correspond to the DAC core they feed by default, in Configuration 0)

includes a modulator switch that allows the user to route the

desired I and/or Q sample to one or all DAC cores. NCOx are

located near the output of their respective main digital datapaths.

The switch has four configurations, as shown in Figure 81 through

Figure 84. Some configurations bypass the NCO altogether and

route the complex I and Q samples from each datapath to the DAC

core(s), whereas other modes route the output of the NCOs instead.

Of particular interest may be Configuration 2, shown in Figure 83,

where I samples are sent to DAC0 and Q samples are sent to DAC1,

to operate the AD9174 as a traditional IF DAC. Configuration 3

routing also depends on whether NCO1 and/or DAC1 is enabled.

The configurations are set via Register 0x112, Bits[5:4] and are

paged by the MAINDAC_PAGE register control.

NCO

DAC0 I DATA

DAC0 NCO REAL DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

DAC1 NCO REAL DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

Figure 81. Configuration 0—DAC0 = I0, DAC1 = I1

÷2

NCO

DAC0 I DATA

÷2

SUM OF I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

SUM OF Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

Figure 82. Configuration 1, CMPLX_MOD_DIV2_DISABLE = 0—DAC0 = I0 + I1, DAC1 = Q0 + Q1

NCO

DAC0 I DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

DAC0 Q DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

Figure 83. Configuration 2—DAC0 = I0, DAC1 = Q0

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