AD9174 datasheet(43/164 Pages) AD

43 / 164 page

Data Sheet

AD9174

Rev. A | Page 43 of 164

Link Delay

The link delay of a JESD204B system is the sum of the fixed and

variable delays from the transmitter, channel, and receiver as

shown in Figure 63.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B specifica-

tion states that the LMFC period must be larger than the maximum

link delay. For the AD9174, this is not necessarily the case. Instead,

the AD9174 use a local LMFC for each link (LMFCRx) that can

be delayed from the SYSREF± aligned LMFC. Because the

LMFC is periodic, this delay can account for any amount of

fixed delay. As a result, the LMFC period must only be larger

than the variation in the link delays, and the AD9174 can achieve

proper performance with a smaller total latency. Figure 64 and

Figure 65 show a case where the link delay is greater than an LMFC

period. The link delay can be accommodated by delaying LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 64. Link Delay > LMFC Period Example

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC_DELAY

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 65. LMFC_DELAY_x to Compensate for Link Delay > LMFC

The method to select the LMFCDel (Register 0x304) and

LMFCVar (Register 0x306) variables is described in the Link

Delay Setup Example, with Known Delays section and the Link

Delay Setup Example, Without Known Delay section. The setting

for LMFCDel must not equal or exceed the number of PCLK

cycles per LMFC period in the current mode. Similarly, LMFCVar

must not exceed the number of PCLK cycles per LMFC period in

the current mode or be set to <12 (whichever value is smaller).

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then, LMFCVar

is written into the receive buffer delay (RBD) to absorb all link

delay variation. This write ensures that all data samples arrived

before reading. By setting these to fixed values across runs and

devices, deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from one frame clock cycle to /K/ frame clock cycles, and the

RBD of the AD9174 takes values from 0 PCLK cycle to 12 PCLK

cycles. As a result, up to 12 PCLK cycles of total delay variation

can be absorbed. LMFCVar and LMFCDel are both in PCLK

cycles. The PCLK factor, or number of frame clock cycles per

PCLK cycle, is equal to 4/f. For more information on this

relationship, see the Clock Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

to Register 0x306 for all devices in the system.

Link Delay Setup Example, with Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 66 is demonstrated in the following

steps. This example is in Subclass 1 to achieve deterministic latency,

and the example uses the case for F = 2. Therefore, the number of

PCLK cycles per multiframe = 16. Because PCBFixed << PCLK

Period, PCBFixed is negligible in this example and not included

in the calculations.

Find the receiver delays using Table 6.

RxFixed = 13 PCLK cycles

RxVar = 2 PCLK cycles

Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

gigabit transceiver on a Virtex-6 FPGA) states that the

delay is 56 ± 2 byte clock cycles.

Because the PCLK rate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PCLK cycles are calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(13 + 13.5 + 0)

= floor(26.5)

MinDelayLane = 26

Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(13 + 2 + 13.5 + 1 + 0)

= ceiling(29.5)

MaxDelayLane = 30

Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (30 + 1) − (26 − 1) = 31 − 25

LMFCVar = 6 PCLK cycles

Calculate LMFCDel as follows:

LMFCDel = (MinDelay − 1) % (PCLKsperMF)

= ((26 − 1)) % 16

= 25 % 16

LMFCDel = 9 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

AD9174 Datasheet(PDF) 43 Page - Analog Devices

AD9174 Datasheet(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL