AD9174 datasheet(48/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 48 of 164

9. Read the PRBS test results from the PRBS status registers:

a. Each bit of PHY_PRBS_PASS (Register 0x31D)

corresponds to one SERDES lane (0 = fail, 1 = pass).

The default value following a reset is pass. To confirm

that the reported results are not a false positive, force a

fail condition on one or all of the lanes before running

a lengthy BER test. Either temporarily disable some or

all of the lanes for which the test was previously enabled

and confirm that the test fails, or select a PRBS pattern

of the incorrect type in Step 2 to observe failures on all

lanes. Then, reconfigure the test appropriately and run

the test to accumulate BER results.

b. The number of PRBS errors seen on each failing lane

can be read by writing the lane number to check (0 to

7) in PHY_SRC_ERR_CNT (Register 0x316, Bits[6:4])

and reading the PHY_PRBS_ERR_CNT_xBITS

(Register 0x31A to Register 0x31C). The maximum

error count is 224 − 1. If all bits of Register 0x31A to

the selected lane is exceeded.

Table 31. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting (Register 0x316,

Bits[3:2])

PRBS Pattern

0b00 (default)

PRBS7

0b01

PRBS15

0b10

PRBS31

Internal PRBS7 Generator

The AD9174 integrates one internal PRBS7 generator that can

be used to test the JESD204B PHYs without an external PRBS

data input from a JESD204B transmitter. Although this approach

only confirms the portion of the PHY internal to the AD9174, it

does confirm that both the PRBS checker and internal clock

domains are running and are configured correctly. The internal

PRBS test is ideally followed by a more thorough, external PHY

PRBS test, in which case the pattern is sourced by a JESD204B

transmitter device.

The process for configuring the internal PRBS7 generator on

the AD9174 is as follows:

1. Set the EQ_BOOST_PHYx bits (Register 0x240, Bits[7:0]

and Register 0x241, Bit[7:0]) to 0.

2. Set SEL_IF_PARDATAINV_DES_RC_CH bits

(Register 0x234, Bits[7:0]) to 0 to make sure lanes not

inverted.

3. Enable the loop back test for all lanes being tested by

writing to EN_LBT_DES_RC_CH (Register 0x250). Each

bit of Register 0x250 enables the loop back test for the

corresponding lane. For example, writing a 1 to Bit 0 enables

the test for Physical Lane 0.

4. For halfrate, set EN_LBT_HALFRATE_DES_RC

(Register 0x251, Bit 1) to 1. Otherwise, set this bit to 0.

5. Toggle INIT_LBT_SYNC_DES_RC (Register 0x251, Bit 0)

from 0 to 1 then back to 0.

6. Refer to the PRBS Testing section for information on how

to configure the PRBS checker for a PRBS7 test.

Transport Layer Testing

The JESD204B receiver in the AD9174 supports the short

transport layer (STPL) test as described in the JESD204B

standard. Use this test to verify the data mapping between the

JESD204B transmitter and receiver. To perform this test, this

function must be implemented and enabled in the logic device.

Before running the test on the receiver side, the link must be

established and running without errors.

The STPL test ensures that each sample from each converter is

mapped appropriately according to the number of converters

(M) and the number of samples per converter (S). As specified

in the JESD204B standard, the converter manufacturer specifies

the test samples that are transmitted. Each sample must have a

unique value. For example, if M = 2 and S = 2, four unique

samples are transmitted repeatedly until the test is stopped. The

expected sample must be programmed into the device and the

expected sample is compared to the received sample one sample

at a time until all are tested. The process for performing this test

on the AD9174 is described as follows:

1. Synchronize and establish a JESD204B link between the

transmitter and the AD9174.

2. Enable the STPL test at the JESD204B transmitter.

Depending on JESD204B mode, there may be up to six

data streams per link, to feed up to three complex sub-

channels (M = 6), and each frame can contain up to eight

samples (S = 8).

3. Configure the SHORT_TPL_REF_SP_MSB bits

(Register 0x32E) and the SHORT_TPL_REF_SP_LSB bits

(Register 0x32D) to match one of the samples within a

single frame. For N = 12 modes, the integer value of the

expected sample is multiplied by 16 (binary, 4-bit shift

operation).

4. If testing a dual-link JESD204B, set SHORT_TPL_LINK_SEL

(Register 0x32F, Bit 7) to select whether Link 0 (DAC0

datapath(s)) or Link 1 (DAC1 datapath(s)) is tested.

5. Set SHORT_TPL_CHAN_SEL (Register 0x32C, Bits[3:2])

to select the channel.

6. Set SHORT_TPL_IQ_PATH_SEL (Register 0x32F, Bit 6) to

select the I or Q stream of the channel under test.

7. Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to

select which sample within each frame is expected to have

the value indicated in Step 3.

8. Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1.

9. Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to

1, then back to 0.

10. Wait for the desired time. The desired time is calculated as

1/(sample rate × BER). For example, given BER = 1 × 10−10

and a sample rate = 1 GSPS, the desired time = 10 sec.

11. Read the test result at SHORT_TPL_FAIL (Register 0x32F,

Bit 0).

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