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AD9174

Data Sheet

Rev. A | Page 28 of 164

THEORY OF OPERATION

The AD9174 is a 16-bit, dual RF DAC with a high speed JESD204B

SERDES interface, compliant with Subclass 0 and Subclass 1

operation. Figure 1 shows a functional block diagram of the

AD9174. Each DAC core has three individually bypassable

channels that support up to 1.575 GSPS of complex data rate

input per channel. The JESD204B interface can be configured

for either single-link or a dual-link operation, in which each of

the eight high speed serial ports can carry data at a maximum of

15.4 Gbps to the channel datapaths, referred to as channelizers.

Compared to either LVDS or CMOS interfaces, the SERDES

interface simplifies pin count, board layout, and input clock

requirements to the device.

The local clock for the SERDES interface is derived from the

device clock (CLKIN± pins) as required by the JESD204B

specification. The device clock either acts as a reference for the

on-chip PLL to provide a DAC clock, or the PLL can be bypassed

and the DAC clock can be provided directly from a high fidelity,

external clock source. The SERDES interface can be configured

to operate in one, two, three, four, or eight lane per link modes,

depending on the required input data rate. In dual-link operation,

each link can occupy a maximum of four lanes each.

The digital datapath of the AD9174 includes bypassable (1×)

interpolation blocks in both the channel datapaths and the main

datapaths. Depending on the desired mode, there are also 2×,

3×, 4×, 6×, and 8× interpolation options for the channel datapaths,

and 2×, 4×, 6×, 8×, and 12× interpolation options for the main

datapaths. See Table 13 for a summary of the various supported

processing modes, as well as the associated interpolation options.

Unless 1× interpolation (bypass) is selected, each channel digital

datapath allows the user to individually control the gain stages

and NCO blocks at each channel. The NCO blocks have a 48-bit

modulus NCO option to enable digital frequency shifts of signals

with near infinite precision. At the end of the three channelizer

datapaths, there is a summation node that combines the three

channelizers together at a maximum of 1.575 GSPS, sent as an

input to the respective main DAC datapaths for further digital

processing.

Each main DAC datapath contains an optional power amplifier

(PA) protection block, a main datapath interpolation block, a

main NCO with an optional modulus feature, and a ramp-up/

ramp-down gain block that is fed by the PA protection block.

Additionally, there is an optional calibration tone feature, as

well as four modulator switch modes that are part of the main

NCO block.

Each NCO can operate as a standalone NCO in direct digital

synthesis (DDS) mode. The level of the NCO tone can be either

individually assigned by providing digital data from the SERDES

interface, or collectively assigned to all NCOs using a SPI-

programmable register. The frequency can be individually

controlled.

The AD9174 is also capable of FFH, which allows quick hopping

between 31 additional NCOs, each operating at a 32-bit precision.

Various modes of operation exist where either coherence or

phase continuity can be maintained between hops. Only a single

SPI write is required to hop to the next frequency, assuming

each frequency tuning word (FTW) is preloaded.

The AD9174 is also capable of multichip synchronization that

can both synchronize multiple DACs and establish a constant

and deterministic latency (latency locking) path for the DACs.

The latency for each DAC remains constant to within several

DAC clock cycles from link establishment to link establishment.

An external alignment signal (SYSREF±) makes the AD9174

JESD204B Subclass 1 compliant. Several methods of SYSREF±

signal handling are available for use in the system.

An SPI port configures the various functional blocks and monitors

their status. The various functional blocks and the data interface

must be set up in a predetermined sequence for proper operation

(see the Start-Up Sequence section). Simple SPI initialization

routines set up the JESD204B link and are included in the

AD9174-FMC-EBZ evaluation board package. This data sheet

describes the various blocks of the AD9174 in detail. Descriptions

of the JESD204B interface, control parameters, and various

registers to set up and monitor the device are provided. The

recommended start-up routine reliably sets up the data link.

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