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AD9174

Data Sheet

Rev. A | Page 56 of 164

Unlike other NCO control registers, the FTW registers are not

applied to the NCO block immediately upon writing the control

of DDSC_FTW_LOAD_REQ (Register 0x131, Bit 0). After an

update request, DDSC_FTW_LOAD_ACK (Register 0x131, Bit 1)

must indicate a status high to acknowledge that the FTW has

been updated.

The DDSC_SEL_SIDEBAND bit (Register 0x130, Bit 1 = 0b1)

is a convenience bit that controls whether the lower- or upper-

sideband of the modulated data is used, which is equivalent to

flipping the sign of the FTW.

INTERPOLATION

NCO

–1

COS(ωn + θ)

SIN(ωn + θ)

I DATA

Q DATA

DDSC_FTW[47:0]

DDSC_SEL_SIDEBAND

OUT_I

OUT_Q

–

DDSC_NCO_PHASE_OFFSET

[15:0]

Figure 74. NCO Modulator Block Diagram

Channel Modulus NCO Mode (Direct Digital Synthesis

(DDS) Mode)

Each 48-bit channel NCO can also be used in a dual modulus

mode to create fractional frequencies beyond the 48-bit accuracy

that integer mode provides, which may be of interest in applications

where the NCO is running for prolonged periods of time without

being reset, thus possibly resulting in a noticeable phase drift

relative to other clocks in the system, even given the small

initial frequency error of the 48-bit, integer NCO. The modulus

mode is enabled by programming the DDSC_MODULUS_EN bit

in the DDSC_DATAPATH_CFG register to 1 (Register 0x130,

Bit 2 = 0b1).

The frequency ratio for the programmable modulus DDS is

very similar to that of the typical accumulator-based DDS. The

only difference is that N is not required to be a power of two (as

for integer NCOs) for the programmable modulus, but can be

an arbitrary integer. In practice, hardware constraints place

limits on the range of values for N. As a result, the modulus

extends the use of the NCO to applications that require exact

rational frequency synthesis. The underlying function of the

programmable modulus technique is to alter the accumulator

modulus.

Implementation of the programmable modulus function within

the AD9174 is such that the fraction, M/N, is expressible by the

following equation. The form of the equation implies a

compound frequency tuning word with X representing the

integer part and A/B representing the fractional part.

CARRIER

NCO CLK

where:

X is the FTW, programmed in Register 0x132 to Register 0x137.

A is programmed in Register 0x140 to Register 0x145.

B is programmed in Register 0x13A to Register 0x13F.

Because X, A, and B are 48-bit words, modulus mode allows the

user to set the NCO output frequency (fCARRIER) with a precision

of (fNCO,CLK)/2(2 ×48).

Programmable Modulus Example

Consider the case in which fNCO,CLK = 1500 MHz and the desired

value of fCARRIER is 150 MHz. This scenario synthesizes an output

frequency that is not a power of two submultiple of the sample

rate, namely fCARRIER = (1/10) fNCO,CLK, which is not possible with

a typical accumulator-based DDS. The frequency ratio, fCARRIER/

fNCO,CLK, leads directly to M and N, which are determined by

reducing the fraction (150,000,000/1,500,000,000) to its lowest

terms, that is,

M/N = 150,000,000/1,500,000,000 = 1/10

Therefore, M = 1 and N = 10.

After calculation, X = 28,147,497,671,065, A = 3, and B = 5.

Programming these values into the registers for X, A, and B

(X is programmed in Register 0x132 to Register 0x137 for

DDSC_FTWx, B is programmed in Register 0x13A to

programmed in Register 0x140 to Register 0x145 for DDSC_

ACC_DELTAx) causes the NCO to produce an output frequency

of exactly 150 MHz given a 1500 MHz sampling clock. For more

details, refer to the AN-953 Application Note.

NCO Reset

Resetting an NCO is useful when determining the start time

and phase of a particular NCO. Each Channel NCO can be

configured to reset in response to one of several events: a direct

request via SPI (Register 0x131, Bit 0), a change to one of the

FTW register values, or on the next SYSREF± rising edge. The

reset method is controlled by Register 0x131. See the detailed

description for Register 0x131 for more information.

Channel Summing Node

The outputs of the channelizers are combined at the summing

node junction before being routed to the respective main datapath.

The summation of any number of channels being used must not

exceed a value range of ±215 to avoid clipping (binary overflow)

of the 16-bit data samples that are summed into the main datapath.

The maximum data rate for each channel when the channel

interpolation is >1× is limited by the maximum speed of summing

node junction, namely 1.575 GSPS. If the channel datapaths are

bypassed (channel interpolation is 1×), the summing node

block is also bypassed, as shown in Figure 72. Bypassing the

channelizer(s) allows passing data to the main digital datapath

at a higher data rate. See Table 13 for JESD204B modes and the

corresponding maximum data rates.

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