AD9174 datasheet(60/164 Pages) AD

60 / 164 page

AD9174

Data Sheet

Rev. A | Page 60 of 164

Table 46. Main Datapath NCO FTW Registers

Address

Value

Description

0x114

DDSM_FTW[7:0]

8 LSBs of FTW

0x115

DDSM_FTW[15:8]

Next 8 bits of FTW

0x116

DDSM_FTW[23:16]

Next 8 bits of FTW

0x117

DDSM_FTW[31:24]

Next 8 bits of FTW

0x118

DDSM_FTW[39:32]

Next 8 bits of FTW

0x119

DDSM_FTW[47:40]

8 MSBs of FTW

Unlike other NCO control registers, the FTW registers are not

applied to the NCO block immediately on writing the control

rising edge of DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0).

After an update request, DDSM_FTW_LOAD_ACK

(Register 0x113, Bit 1) must indicate a high status to

acknowledge that the FTW is updated.

The DDSC_SEL_SIDEBAND bit Register 0x112, Bit 1 = 0b1)

is a convenience bit that controls whether the lower or upper

sideband of the modulated data is used, which is equivalent to

flipping the sign of the FTW.

INTERPOLATION

NCO

–1

COS(ωn + θ)

SIN(ωn + θ)

I DATA

Q DATA

DDSM_FTW[47:0]

DDSM_SEL_SIDEBAND

OUT_I

OUT_Q

–

DDSM_NCO_PHASE_OFFSET

[15:0]

Figure 79. NCO Modulator Block Diagram, Main Datapath Modulus NCO

Mode (DDS)

Each of the main datapath 48-bit NCOs can also be used in a

dual modulus mode to create fractional frequencies beyond the

48-bit accuracy. The modulus mode is enabled by programming

the DDSM_MODULUS_EN bit in the DDSM_DATAPATH_

CFG register to 1 (Register 0x112, Bit 2 = 0b1).

The main datapath modulus NCOs are of a similar architecture to

the channel modulus NCOs, and the X (FTW), A, and B values are

calculated in a similar manner:

CARRIER

NCO CLK

where:

X is the FTW, programmed in Register 0x114 to Register 0x119.

A is programmed in Register 0x12A to Register 0x12F.

B is programmed in Register 0x124 to Register 0x129.

For more details and examples, see the Channel Modulus NCO

Mode (Direct Digital Synthesis (DDS) Mode) section. The main

datapath NCOs operate at a higher clock rate (fNCO, CLK) than the

channel NCOs, and are addressed from a different set of SPI

registers.

NCO Reset

Resetting the main datapath NCOs can be useful when determ-

ining the start time and phase of an NCO. Each NCO can be

configured to reset in response to one of several events: a direct

request via SPI (Register 0x113, Bit 0), a change to one of the

FTW register values, or on the next SYSREF± rising edge. The

reset method is controlled by Register 0x113. See the detailed

description of Register 0x113 in Table 62 for more information.

Fast Frequency Hopping (FFH)

Each main datapath NCO in the AD9174 has several features

that allow FFH between preconfigured carrier frequencies. The

main 48-bit NCO is a general-purpose NCO, combined with a

bank of 31 FFH NCOs, with 32 bits each.

FFH NCO

Each FFH NCO is implemented within the main 48-bit NCO,

with an associated bank of 31 FTWs located in Register 0x806 to

words that are loaded into the hopping frequency register bank

when the particular NCO is reset. Any of the 32 FTWs can be

selected by a single register write to the HOPF_SEL bits in the

DDSM_HOPF_CTRL register (Register 0x800, Bits[4:0]). The

manner in which the phase of a particular NCO transitions as it

hops between carrier frequencies is determined by the NCO

frequency change mode. These modes include phase continuous

hopping, phase discontinuous hopping, and phase coherent

hopping. The hopping modes are controlled by Register 0x800,

Bits[7:6], as described in Table 47.

Table 47. NCO Frequency Change Mode

Description

0b00

Phase continuous switch

0b01

Phase discontinuous switch (reset

NCO accumulator)

0b10

Phase coherent switch

In phase discontinuous mode, the FTW of the NCO is updated

and the phase accumulator is reset, resulting in an abrupt phase

change each time the NCO hops to a new frequency. The

discontinuous phase may result in an undesirable glitch at the

transition point. Alternatively, in phase continuous switching,

the frequency tuning word of the NCO is updated, while the

main phase accumulator maintains count throughout the

update, resulting in a smooth phase transition between carrier

frequencies.

AD9174 Datasheet(PDF) 60 Page - Analog Devices

AD9174 Datasheet(HTML) 60 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL