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Data Sheet

AD9174

Rev. A | Page 67 of 164

INTERRUPT REQUEST OPERATION

The AD9174 provides an interrupt request output signal (IRQ)

on Pin D9 (IRQ0) and Pin E9 (IRQ1) that can be used to notify an

external host processor of significant device events. The IRQ

output can be switched between the IRQ0 pin or the IRQ1 pin by

setting the corresponding bit for the IRQ signal in Register 0x028,

assertion of the interrupt, query the device to determine the

precise event that occurred. The IRQx pins are open-drain,

active low outputs. Pull the IRQx pins high, external to the

device. These pins can be tied to the interrupt pins of other

devices with open-drain outputs to wire. OR these pins

together.

Figure 87 shows a simplified block diagram of how the IRQx

blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE

signal is set to 0. If IRQ_EN is high, any rising edge of EVENT

causes the INTERRUPT_SOURCE signal to be set high. If any

INTERRUPT_SOURCE signal is high, the IRQx pin is pulled

low. INTERRUPT_SOURCE can be reset to 0 by either an

IRQ_RESET signal or a DEVICE_RESET signal.

Depending on the STATUS_MODE signal, EVENT_STATUS

reads back an event signal or an INTERRUPT_SOURCE signal.

The AD9174 has several IRQ register blocks that can monitor

up to 86 events, depending on the device configuration. Certain

details vary by IRQ register block, as described in Table 49.

Table 50 shows the source registers of the IRQ_EN, IRQ_RESET,

and STATUS_MODE signals in Figure 87, as well as the address

where EVENT_STATUS is read back.

Table 49. IRQ Register Block Details

Event

Reported

EVENT_STATUS

0x020 to 0x27

Per chip

INTERRUPT_SOURCE if IRQ is

enabled; if not, it is an event

0x4B8 to 0x4BB;

0x470 to 0x473

Per link and

lane

INTERRUPT_SOURCE if IRQ is

enabled; if not, 0

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of

event flags that require host intervention or monitoring. Enable

the events that require host action so that the host is notified

when they occur. For events requiring host intervention upon

IRQ activation, run the following routine to clear an interrupt

request:

Read the status of the event flag bits that are being monitored.

Disable the interrupt by writing 0 to IRQ_EN.

Read the event source.

Perform any actions that may be required to clear the cause

of the event. In many cases, no specific actions may be

required.

Verify that the event source is functioning as expected.

Clear the interrupt by writing 1 to IRQ_RESET.

Enable the interrupt by writing 1 to IRQ_EN.

IRQ_EN

EVENT

DEVICE_RESET

EVENT_STATUS

INTERRUPT_SOURCE

IRQ_EN

STATUS_MODE

OTHER

INTERRUPT

SOURCES

IRQ

IRQ_RESET

Figure 87. Simplified Schematic of IRQx Circuitry

Table 50. IRQ Register Block Address of IRQ Signal Details

Block

Address of IRQ Signals1

IRQ_EN

IRQ_RESET

STATUS_MODE

EVENT_STATUS

0x020 to

0x023

0x020 to 0x023; R/W per chip

0x024 to 0x027; per chip

STATUS_MODE= IRQ_EN

0x024 to 0x027; R per chip

0x4B8 to

0x4BB

0x4B8, 0x4B9; W per error type

0x4BA, 0x4BB; W per error type

Not applicable, STATUS_MODE = 1

0x4BA, 0x4BB; W per chip

0x470 to

0x473

0x470 to 0x473; W per error type

0x470 to 0x473; W per link

Not applicable, STATUS_MODE = 1

0x470 to 0x473; W per link

1 R is read, W is write, and R/W is read/write.

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