AD9174 datasheet(102/164 Pages) AD

102 / 164 page

AD9174

Data Sheet

Rev. A | Page 102 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x094

PLL_CLK_DIV

[7:2]

RESERVED

Reserved.

0x0

PLL_VCO_DIV3_EN

Enable PLL output clock divide by 3.

0x0

R/W

PLL_VCO_DIV2_EN

Enable PLL output clock divide by 2.

0x0

R/W

DAC clock = PLL VCO clock frequency.

DAC clock = PLL VCO clock frequency ÷ 2.

0x095

PLL_BYPASS

[7:1]

RESERVED

Reserved.

0x0

PLL_BYPASS

Enable direct clocking (bypassing the PLL

clock).

0x0

R/W

Use the internal PLL to generate the DAC

clock.

Bypass the PLL and directly clock with the

DAC clock frequency.

0x09A

NVM_CTRL

PD_BGR

Bias power-down. Set this bit to 1 to

power down the internal bias.

0x0

R/W

[6:0]

RESERVED

Reserved.

0x0

R/W

0x0C0

DELAY_LINE_PD

[7:6]

RESERVED

Reserved.

0x0

DLL_CTRL0B

DLL control. Set this bit to 0 to power up

the delay line during the device

configuration sequence.

0x1

R/W

DLL_CTRL0A

DLL control. Set this bit to 0 to power up

the delay line during the device

configuration sequence.

0x1

R/W

[3:1]

RESERVED

Reserved.

0x0

DLL_PD

Power down delay line. Set this bit to 0 to

power up the delay line during the device

configuration sequence.

0x1

R/W

Power up and enable the delay line.

Power down and bypass the delay line.

0x0C1

DLL_CTRL0

[7:6]

DLL_CTRL1C

DAC control setting. Set this control to 1

for optimal performance.

0x1

R/W

DLL_CTRL1B

DLL control search mode. If the DAC

frequency is <4.5 GHz, set this bit to 0;

otherwise, set this bit to 1.

0x1

R/W

[4:3]

DLL_CTRL1A

DLL control search direction. Set this

control to 1 for optimal performance.

0x2

R/W

[2:1]

RESERVED

Reserved.

0x0

DLL_ENABLE

DLL controller enable.

0x0

R/W

Disable DLL.

Enable DLL.

0x0C3

DLL_STATUS

[7:1]

RESERVED

Reserved.

0x0

DLL_LOCK

DLL lock indicator. This control reads back

1 if the DLL locks.

0x0

0x0C7

DLL_READ

[7:1]

RESERVED

Reserved.

0x0

DLL_READ_EN

Enable DLL readback status. A transition of

0 to 1 updates the lock status bit readback

in Register 0x0C3.

0x0

R/W

0x0CC

DLL_FINE_DELAY0

[7:6]

RESERVED

Reserved.

0x0

[5:0]

DLL_FINE_DELAY0

DLL delay control.

0x0

R/W

0x0CD

DLL_FINE_DELAY1

[7:6]

RESERVED

Reserved.

0x0

[5:0]

DLL_FINE_DELAY1

DLL delay control.

0x0

R/W

0x0DB

DLL_UPDATE

[7:1]

RESERVED

Reserved.

0x0

DLL_DELAY_

UPDATE

DLL update control. A transition from 0 to

1 updates the DLL circuitry with the

current register control settings.

0x0

R/W

AD9174 Datasheet(PDF) 102 Page - Analog Devices

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