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AD9174 Datasheet(PDF) 105 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 105 Page - Analog Devices

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Data Sheet
AD9174
Rev. A | Page 105 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x113
DDSM_FTW_
UPDATE
7
RESERVED
Reserved.
0x0
R
[6:4]
DDSM_FTW_REQ_
MODE
Frequency tuning word automatic update
mode. This control is paged by the
MAINDAC_PAGE bits in Register 0x008.
0x0
R/W
000
No automatic requests are generated
when the FTW registers are written.
001
Automatically generates a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[7:0] are
written.
010
Automatically generates a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[15:8] are
written.
011
Automatically generates a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[23:16]
are written.
100
Automatically generates a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[31:24]
are written.
101
Automatically generate a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[39:32] is
written.
110
Automatically generates a DDSM_FTW_
LOAD_REQ after DDSM_FTW Bits[47:40]
are written.
3
RESERVED
Reserved.
0x0
R
2
DDSM_FTW_
LOAD_SYSREF
Uses the next rising edge of SYSREF± to
trigger FTW load and reset. This bit also
loads the calibration tone FTW, as well as
the main NCO FTW on a rising edge
detection. This control is paged by the
MAINDAC_PAGE bits in Register 0x008.
0x0
R/W
1
DDSM_FTW_
LOAD_ACK
Frequency tuning word update acknow-
ledge. This bit reads back 1 if the FTW and
phase offset word is loaded properly. This
control is paged by the MAINDAC_PAGE bits
in Register 0x008.
0x0
R
0
FTW is not loaded.
1
FTW is loaded.
0
DDSM_FTW_
LOAD_REQ
Frequency tuning word update request
from the SPI. This bit also loads the calibra-
tion tone FTW, as well as the main NCO
FTW on a rising edge detection. This control
is paged by the MAINDAC_PAGE bits in
Register 0x008.
0x0
R/W
0
Clear DDSM_FTW_LOAD_ACK.
1
0 to 1 transition loads the FTW.
0x114
DDSM_FTW0
[7:0]
DDSM_FTW[7:0]
Sets the main datapath NCO FTW. If
DDSM_MODULUS_EN is low, the main
datapath NCO frequency = fDAC × (DDSM_
FTW/248). If DDSM_MODULUS_EN is high,
the main datapath NCO frequency = fDAC ×
(DDSM_FTW + DDSM_ACC_DELTA/DDSM_
ACC_MODULUS)/248. DDSM_ACC_DELTA
must be >0. DDSM_ACC_DELTA must be
>DDSM_ACC_MODULUS. This control is
paged by the MAINDAC_PAGE bits in
Register 0x008.
0x0
R/W



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