Electronic Components Datasheet Search
  English  ▼

X  

AD9174 Datasheet(PDF) 103 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 103 Page - Analog Devices

Back Button AD9174 Datasheet HTML 99Page - Analog Devices AD9174 Datasheet HTML 100Page - Analog Devices AD9174 Datasheet HTML 101Page - Analog Devices AD9174 Datasheet HTML 102Page - Analog Devices AD9174 Datasheet HTML 103Page - Analog Devices AD9174 Datasheet HTML 104Page - Analog Devices AD9174 Datasheet HTML 105Page - Analog Devices AD9174 Datasheet HTML 106Page - Analog Devices AD9174 Datasheet HTML 107Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 103 / 164 page
background image
Data Sheet
AD9174
Rev. A | Page 103 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x0FF
MOD_SWITCH_
DEBUG
[7:2]
RESERVED
Reserved.
0x0
R
1
CMPLX_MOD_
DIV2_DISABLE
Disables the divide by 2 block in the mod-
ulator switch path. Set to 1 to bypass the
divide by 2 block. This control is paged by
the MAINDAC_PAGE bits in Register 0x008.
0x0
R/W
0
RESERVED
Reserved.
0x0
R
0x100
DIG_RESET
[7:1]
RESERVED
Reserved.
0x0
R
0
DIG_DATAPATH_PD
Holds all digital logic (SERDES digital,
digital clock generation, and digital
datapath) in reset until clock tree is stable.
0x1
R/W
0
Normal operating mode.
1
Holds the digital logic in reset. Must be
released (set to 0) after clocks to the chip
are stable (PLL and DLL blocks are locked)
to use the digital datapath.
0x110
JESD_MODE
7
MODE_NOT_IN_
TABLE
Programmed JESD204B mode and interpola-
tion mode combination is not valid. Select
a different combination.
0x0
R
6
COM_SYNC
Combine the
A
SYNCOUTx±E
A
signals in dual
link case.
0x0
R/W
[5:0]
JESD_MODE
Sets the JESD204B mode configuration.
See Table 13 for the JESD204B supported
operating modes and compatible interpola-
tion rates. Bit 5 of this control determines
single link (set to 0) or dual link (set to 1).
Bits[4:0] set the desired JESD204B mode
according to Table 13.
0x20
R/W
0x111
INTRP_MODE
[7:4]
DP_INTERP_MODE
Sets main datapath interpolation rate. See
Table 13 for the JESD204B supported
operating modes and compatible JESD204B
modes and channel interpolation rates.
0x8
R/W
0x1
1×.
0x2
2×.
0x4
4×.
0x6
6×.
0x8
8×.
0xC
12×.
[3:0]
CH_INTERP_MODE
Sets channel interpolation rate. See Table 13
for the JESD204B supported operating
modes and compatible JESD204B modes
and main datapath interpolation rates.
0x4
R/W
0x1
1×.
0x2
2×.
0x3
3×.
0x4
4×.
0x6
6×.
0x8
8×.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com