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AD9174 Datasheet(PDF) 103 Page - Analog Devices |
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AD9174 Datasheet(HTML) 103 Page - Analog Devices |
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103 / 164 page ![]() Data Sheet AD9174 Rev. A | Page 103 of 164 Addr. Name Bits Bit Name Settings Description Reset Access 0x0FF MOD_SWITCH_ DEBUG [7:2] RESERVED Reserved. 0x0 R 1 CMPLX_MOD_ DIV2_DISABLE Disables the divide by 2 block in the mod- ulator switch path. Set to 1 to bypass the divide by 2 block. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0 RESERVED Reserved. 0x0 R 0x100 DIG_RESET [7:1] RESERVED Reserved. 0x0 R 0 DIG_DATAPATH_PD Holds all digital logic (SERDES digital, digital clock generation, and digital datapath) in reset until clock tree is stable. 0x1 R/W 0 Normal operating mode. 1 Holds the digital logic in reset. Must be released (set to 0) after clocks to the chip are stable (PLL and DLL blocks are locked) to use the digital datapath. 0x110 JESD_MODE 7 MODE_NOT_IN_ TABLE Programmed JESD204B mode and interpola- tion mode combination is not valid. Select a different combination. 0x0 R 6 COM_SYNC Combine the A SYNCOUTx±E A signals in dual link case. 0x0 R/W [5:0] JESD_MODE Sets the JESD204B mode configuration. See Table 13 for the JESD204B supported operating modes and compatible interpola- tion rates. Bit 5 of this control determines single link (set to 0) or dual link (set to 1). Bits[4:0] set the desired JESD204B mode according to Table 13. 0x20 R/W 0x111 INTRP_MODE [7:4] DP_INTERP_MODE Sets main datapath interpolation rate. See Table 13 for the JESD204B supported operating modes and compatible JESD204B modes and channel interpolation rates. 0x8 R/W 0x1 1×. 0x2 2×. 0x4 4×. 0x6 6×. 0x8 8×. 0xC 12×. [3:0] CH_INTERP_MODE Sets channel interpolation rate. See Table 13 for the JESD204B supported operating modes and compatible JESD204B modes and main datapath interpolation rates. 0x4 R/W 0x1 1×. 0x2 2×. 0x3 3×. 0x4 4×. 0x6 6×. 0x8 8×. |
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