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DS3173N Datasheet(PDF) 46 Page - Dallas Semiconductor |
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DS3173N Datasheet(HTML) 46 Page - Dallas Semiconductor |
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46 / 232 page ![]() DS3171/DS3172/DS3173/DS3174 46 of 230 Figure 8-25. Clear Status Latched Register on Read D[15:0] A[10:1] A[0]/BSWAP 0x1C0 0xFFFF 0x1C0 0x0000 Z Z Z Z RD WR CS RDY Figure 8-26. Clear Status Latched Register on Write D[15:0] A[10:1] A[0]/BSWAP 0x1C0 0xFFFF 0x1C0 0x5555 0x1C0 0xAAAA Z Z Z Z Z Z RD WR CS RDY Figure 8-27 and Figure 8-28show exaggerated views of the Ready Signal to describe the difference in access times to write or read to or from various memory locations on the DS317x device. Some registers will have a faster access time than others will and if needed, the user can implement the RDY signal to maximize efficiency of read and write accesses. |
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