DS3173N datasheet(96/232 Pages) DALLAS

96 / 232 page

DS3171/DS3172/DS3173/DS3174

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The receive direction performs packet processing and stores the packet data in the FIFO. It removes packet data

from the FIFO and outputs the packet data to the microprocessor via the register interface.

The transmit direction inputs the packet data from the microprocessor via the register interface and stores the

packet data in the FIFO. It removes the packet data from the FIFO and performs packet processing.

The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB

last. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8 (LSB).

However, when a byte is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is

stored in the highest numbered bit (7). This is to differentiate between a byte in a register and the corresponding

byte in a signal.

Refer to Figure 10-20 for the location of HDLC controllers within the DS3174,3,2,1 devices.

Figure 10-20. HDLC Controller Block Diagram

10.7.2 Features

Programmable inter-frame fill – The inter-frame fill between packets can be all 1’s or flags.

Programmable FCS generation/monitoring – An FCS-16 can be generated and appended to the end of the

packet, and the FCS can be checked and removed from the end of the packet.

Programmable bit reordering – The packet data can be can be output MSB first or LSB first from the FIFO.

Programmable data inversion – The packet data can be inverted immediately after packet processing on the

transmit, and immediately before packet processing on the receive.

Fully independent transmit and receive paths

Fully independent Line side and register interface timing – The data storage can be read from or written to

via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to

via the line side while all microprocessor interface clocks and signals are inactive.

10.7.3 Transmit FIFO

The Transmit FIFO block contains memory for 256 bytes of data with data status information and controller circuitry

for reading and writing the memory. The Transmit FIFO controller functions include filling the memory, tracking the

memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow

conditions. The Transmit FIFO receives data and status from the microprocessor interface, and stores the data

along with the data status information in memory. The Transmit Packet Processor reads the data and data status

information from the Transmit FIFO. The Transmit FIFO also outputs FIFO fill status (empty/data storage

available/full) via the microprocessor interface. All operations are byte based. The Transmit FIFO is considered

empty when its memory does not contain any data. The Transmit FIFO is considered to have data storage

available when its memory has a programmable number of bytes or more available for storage. The Transmit FIFO

is considered full when it does not have any space available for storage. The Transmit FIFO accepts data from the

DS3/E3

Transmit

LIU

IEEE P1149.1

JTAG Test

Access Port

Microprocessor

Interface

HDLC

FEAC

DS3 / E3

Transmit

Formatter

DS3 / E3

Receive

Framer

Trail

Trace

Buffer

DS3/E3

Receive

LIU

TAIS

TUA1

Clock Rate

Adapter

TX BERT

RX BERT

UA1

GEN

B3ZS/

HDB3

Encoder

B3ZS/

HDB3

Decoder

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