DS3173N datasheet(37/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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Figure 8-2. TX Line IO HDB3 Functional Timing Diagram

TLCLK

TPOS

TNEG

(TX DATA)

HDB3 CODEWORD

(TX LINE)

TXP

TXN

0 V

BIAS V

8.3.1.2

B3ZS/HDB3/AMI Mode Receive Pin Functional Timing

There is no suggested time alignment between the RXPn, RXNn and RX LINE signals and the RLCLKn clock

signal. The RX DATA signal is not an always readily available signal, it is meant to represent the data value of the

other signals. The signal on RSERn will be the same as the RX DATA signal except delayed.

The RXPn and RXNn pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is enabled.

The RPOSn, RNEGn and RLCLKn pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU

is disabled.

The RPOSn and RNEGn signals are sampled at the rising edge of the reference clock signal if the clock pin is not

inverted; otherwise they are sampled at the negative edge. The RLCLKn clock pin is the clock reference used for

the RPOSn and RNEGn signals. The RPOSn and RNEGn pins can be inverted.

RXPn and RXNn are differential analog input pins. They are biased around ½ VDD and pulse above and below the

bias voltage by about 1 Volt with zero cable length. These signals are connected to the windings of a 1:2 step up

transformer and the other winding of the transformer is connected to the RX LINE signal. The RX LINE signal is a

bipolar signal that pulses about 1 Volt positive and 1 Volt negative above and below ground (0 volts) with zero

cable length. See Figure 1-1 for a diagram of the external connections.

Figure 8-3 and Figure 8-4 show the relationship between the analog and the digital outputs.

Figure 8-3. RX Line IO B3ZS Functional Timing Diagram

RLCLK

RPOS

RNEG

(RX DATA)

B3ZS CODEWORD

(RX LINE)

RXP

RXN

0 V

BIAS V

DS3173N Datasheet(PDF) 37 Page - Dallas Semiconductor