DS3173N datasheet(33/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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PIN NAME

TYPE

PIN DESCRIPTION

the clock. The signal is typically referenced to the RCLKOn receive clock output pin,

but it can be referenced to the RLCLKn clock input pin.

This signal can be inverted.

RDENn: When the port framer is configured for the DS3 or E3 framed modes and the

RDENn pin function is enabled, this signal is used to indicate the DS3/E3 payload bit

positions of the data on the RSERn pin. The signal goes high during each DS3/E3

payload bit and goes low during each DS3/E3 overhead bit. The signal is updated on

the positive clock edge of the referenced clock pin if the clock pin signal is not

inverted, otherwise it is updated on the falling edge of the clock. The signal is typically

referenced to the RCLKOn receive clock output pin, but it can be referenced to the

RLCLKn clock input pin.

This signal can be inverted.

Microprocessor Interface

D[15:0]

Bi-directional 16 or 8-bit data bus

This bus is tri-state when

RST pin is low or CS pin is high.

D[15:0]: A 16-bit or 8-bit data bus used to input data during register writes, and data

outputs during register reads. The upper 8 bits are not used and never driven in 8-bit

bus mode.

Weak pull up resistors or bus holders should be used for each pin.

A[10:1]

Address bus (minus LSB)

A[10:1]: identifies the specific 16 bit registers, or group of 8 bit registers, being

accessed. A[10] must be tied to ground for the DS3181 and DS3182 versions.

A[0] /

BSWAP

Address bus LSB / Byte Swap

A[0]: This signal is connected to the lower address bit in 8-bit systems. (WIDTH=0)

1 = Output register bits 15:8 on D[7:0], D[15:8] not driven

0 = Output register bits 7:0 on D[7:0], D[15:8] not driven

BSWAP: This signal is tied high or low in 16-bit systems.

(WIDTH=1)

1 = Output register bits 15:8 on D[7:0], 7:0 on D[15:8]

0 = Output register bits 7:0 on D[7:0], 15:8 on D[15:8]

ALE

Address Latch Enable

ALE: This signal is used to latch the address on the A[10:0] pins in multiplexed

address systems. When it is high the address is fed through the address latch to the

internal logic. When it transitions to low, the address is latched and held internally

until the signal goes back high. ALE should be tied high for non-multiplexed address

systems.

Chip Select (active low)

CS: This signal must be low during all accesses to the registers

RD /

Read Strobe (active low) / Data Strobe (active low)

RD: Read Strobe mode (MODE=0):

RD is low during a register read.

DS: Data Strobe mode (MODE=1):

DS is low during either a register read or a write.

WR /

Write Strobe (active low) / R/W Select

WR: Write Strobe mode (MODE=0):

WR is low during a register write.

W: Data Strobe mode (MODE=1):

W is high during a register read cycle, and low during a register write cycle.

RDY

Ready handshake (active low)

RDY: This ready signal is driven low when the current read or write cycle is in

progress. When the current read or write cycle is not ready it is driven high. When

device is not selected, it is not driven.

INT

Interrupt (active low)

This signal is tri-state when

RST pin is low.

DS3173N Datasheet(PDF) 33 Page - Dallas Semiconductor

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